Dmitry Preobrazhensky
cc426402be
[AMDGPU][GFX7][DOC][NFC] Update assembler syntax description
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Summary of changes:
- Enable register tuples with 9, 10, 11 and 12 registers (https://reviews.llvm.org/D138205 ).
- Enable tfe modifier for MUBUF loads (https://reviews.llvm.org/D137783 ).
- Enable abs and neg modifiers for v_cndmask_b32_e64.
- Minor corrections and improvements.
2022-12-13 13:50:40 +03:00
Dmitry Preobrazhensky
9c7e803f2d
[AMDGPU][GFX7][DOC][NFC] Update assembler syntax description
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Summary of changes:
- Updated MUBUF lds syntax (see https://reviews.llvm.org/D124485 ).
- Enabled literals with src0 of v_madak_f32, v_madmk_f32 (see https://reviews.llvm.org/D111067 ).
- Corrected LGKM_CNT description.
- Minor bug fixing.
2022-06-06 15:50:10 +03:00
Dmitry Preobrazhensky
8ea3e9d9a2
[AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description.
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Summary of changes:
- Added f16 omod modifier (bug 51386).
- Corrected names of data types (bug 48638).
- Enabled a16 with most GFX10 MIMG opcodes (see https://reviews.llvm.org/D102231 ).
- Corrected description of integer operands (bug 51130).
- Corrected description of 8-bit DS offsets (bug 51536).
- Improved PERMLANE op_sel description.
- Corrected *SAD* opcode types.
2021-08-27 17:23:20 +03:00
Dmitry Preobrazhensky
b9683d3c53
[AMDGPU][MC][DOC] Updated AMD GPU assembler description.
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Summary of changes:
- Updated to reflect recent changes in assembler;
- Minor bugfixing and improvements.
llvm-svn: 372857
2019-09-25 12:38:35 +00:00
Dmitry Preobrazhensky
1fa7aaf5a7
[AMDGPU][MC][DOC] A fix for build failure in r349370
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llvm-svn: 349375
2018-12-17 18:53:10 +00:00
Dmitry Preobrazhensky
47eb63684d
[AMDGPU][MC][DOC] Updated AMD GPU assembler description
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Stage 2: added detailed description of operands
See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572
llvm-svn: 349368
2018-12-17 17:38:11 +00:00
