1150 Commits

Author SHA1 Message Date
Yeting Kuo
5a57ebcc43 [VP][RISCV] Add vp.abs and RISC-V support.
RISC-V uses ISD::ABS lower method (abs x) -> (smax_vl x (sub_vl 0, x)) for ISD::VP_ABS.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D141033
2023-01-06 15:18:12 +08:00
Yeting Kuo
1e9e1b9cf8 [VP][RISCV] Add vp.ctlz/cttz and RISC-V support.
The patch also adds expandVPCTLZ and expandVPCTTZ to expand vp.ctlz/cttz nodes
and the cost model of vp.ctlz/cttz.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D140370
2023-01-04 15:15:01 +08:00
Gulfem Savrun Yeniceri
70792cd4f8 [LangRef] Add description for nocallback attribute
This patch adds the description for nocallback attribute
that is implemented in https://reviews.llvm.org/D90275.

Differential Revision: https://reviews.llvm.org/D131628
2022-12-22 21:11:59 +00:00
Jessica Paquette
e0f5307f63 Fix indentation in LangRef.rst
Sphinx build was broken.
2022-12-22 11:44:46 -08:00
Jessica Paquette
7ef8f9c972 [IR/MachineOutliner] Add a "nooutline" function attr and respect it
Add `nooutline` + update LangRef to say it exists.

This makes it possible to say "don't outline from this function ever."

We want to be able to toggle whether or not a function should be in the search
set regardless of default behaviour.

Add testcases for the IR Outliner + Machine Outliner.

Also remove an unnecessary check for an empty function in the Machine Outliner.

Differential Revision: https://reviews.llvm.org/D140438
2022-12-22 10:22:08 -08:00
Phoebe Wang
e746a9a600 [Clang] Emit "min-legal-vector-width" attribute for X86 only
This is an alternative way of D139627 suggested by Craig. Creently only X86 backend uses this attribute. Let's just emit for X86 only.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D139701
2022-12-21 11:54:05 +08:00
Joshua Cranmer
e6b02214c6 [IR] Add a target extension type to LLVM.
Target-extension types represent types that need to be preserved through
optimization, but otherwise are not introspectable by target-independent
optimizations. This patch doesn't add any uses of these types by an existing
backend, it only provides basic infrastructure such that these types would work
correctly.

Reviewed By: nikic, barannikov88

Differential Revision: https://reviews.llvm.org/D135202
2022-12-20 11:02:11 -05:00
Qiu Chaofan
6cad2a95fb Fix 'underline too short' failure 2022-12-19 15:29:40 +08:00
Qiu Chaofan
a40ef656d8 [Intrinsic] Rename flt.rounds intrinsic to get.rounding
Address the inconsistency between FLT_ROUNDS_ and SET_ROUNDING SDAG
node. Rename FLT_ROUNDS_ to GET_ROUNDING and add llvm.get.rounding
intrinsic to replace flt.rounds.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D139507
2022-12-19 15:22:39 +08:00
David Goldblatt
61042d2806 [AA][Intrinsics] Add separate_storage assumptions.
This operand bundle on an assume informs alias analysis that the
arguments point to regions of memory that were allocated separately
(i.e. different heap allocations, different allocas, or different
globals).

As a safety measure, we leave the analysis flag-disabled by default.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D136514
2022-12-16 11:05:00 -08:00
Yeting Kuo
ad68586a37 [VP][RISCV] Add vp.ctpop and RISC-V support.
The patch also adds expandVPCTPOP in TargetLowering to expand VP_CTPOP nodes.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D139920
2022-12-14 09:47:44 +08:00
Yeting Kuo
47b9da72e0 [VP][RISCV] Add vp.bitreverse and RISC-V support.
The patch also added function expandVPBITREVERSE to expand ISD::VP_BITREVERSE nodes.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D139697
2022-12-12 10:58:44 +08:00
Yeting Kuo
c6b24ff7bc [LangRef] Fix typo. NFC.
bswap is an unary operation.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D139751
2022-12-10 09:02:08 +08:00
Nikita Popov
b8995342ad [LangRef] Fix typo (NFC) 2022-12-09 08:47:18 +01:00
Alex Richardson
f850035493 [LLParser] Support symbolic address space numbers
This allows the LLParser to also accept "A", "G", and "P" in `addrspace`
usages. "A" will be replaced by the alloca address space defined in the
globals, "G" by the default globals address space and "P" by the program
address space. This makes it easier to write tests that use different
address space and only only vary the RUN: lines. Currently, the only
alternative is to pre-process the sources with a tool such as `sed`

Importantly, these new string values are only accepted in .ll files and
not stored in the bitcode format, so it does not round-trip via llvm-as
and llvm-dis (see newly added test).

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D138789
2022-12-08 20:44:40 +00:00
Yeting Kuo
0f8c761c48 [VP][RISCV] Recommit "Add vp.fshl/fshr and RISC-V support."
This reverts commit 7883e5b061bdbbe8bee5f479ebe911db5045b7e9.

The original commit was reverted that it didn't update test files after D136263
landed. The recommit fixed those.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D139509
2022-12-07 15:58:12 +08:00
Kazu Hirata
7883e5b061 Revert "[VP][RISCV] Add vp.fshl/fshr and RISC-V support."
This reverts commit 70de0e014013b4d97febe6704881a9a8c893d078.

I'm seeing:

Failed Tests (2):
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
  LLVM :: CodeGen/RISCV/rvv/fshr-fshl-vp.ll

Also reported at:

https://lab.llvm.org/buildbot/#/builders/123/builds/14531
2022-12-06 22:27:43 -08:00
Yeting Kuo
70de0e0140 [VP][RISCV] Add vp.fshl/fshr and RISC-V support.
The patch made VectorLegalizer expand ISD::VP_FSHL and ISD::VP_FSHR to
achieve the codegen.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D138379
2022-12-07 12:16:36 +08:00
Matt Arsenault
ba5c26da7c LangRef: Clarify semantics of lround/llround and lrint/llrint 2022-12-06 08:04:01 -05:00
Matt Arsenault
f34fe2a3d2 LangRef: Fix repeated word 2022-11-17 12:54:19 -08:00
Nick Desaulniers
2d3d8c9ad7 [LangRef] remove callbr references from Addresses of BasicBlock section
Since D129288, we no longer use BlockAddress constants as operands of
callbr.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D138080
2022-11-16 09:19:20 -08:00
Yeting Kuo
ed9638c44b [VP][RISCV] Add vp.nearbyint and RISC-V support.
nearbyint has the property to execute without exception.
For not modifying fflags, the patch added new machine opcode
PseudoVFROUND_NOEXCEPT_V that expands vfcvt.x.f.v and vfcvt.f.x.v between a pair
of frflags and fsflags.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D137685
2022-11-16 14:05:35 +08:00
Yeting Kuo
5c3ca10b09 [VP][RISCV] Add vp.bswap and RISC-V support.
The patch also added function expandVPBSWAP to expand ISD::VP_BSWAP nodes.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D137928
2022-11-16 11:36:38 +08:00
Xiaodong Liu
070ab2bb0b [LangRef][LoongArch] Update inline asm constraint code and operand modifier
According to:
https://reviews.llvm.org/D134157
https://reviews.llvm.org/D136841
https://reviews.llvm.org/D136835

Reviewed By: SixWeining

Differential Revision: https://reviews.llvm.org/D137528
2022-11-11 14:25:29 +08:00
Fangrui Song
90ad3e3c02 [IR] Allow available_externally GlobalAlias
GlobalVariable and Function can be available_externally. GlobalAlias is used
similarly. Allowing available_externally is a natural extension and helps
ThinLTO discard GlobalAlias in a non-prevailing COMDAT (see D135427).

For now, available_externally GlobalAlias must point to an
available_externally GlobalValue (not ConstantExpr).

Differential Revision: https://reviews.llvm.org/D137441
2022-11-07 09:03:23 -08:00
Nikita Popov
304f1d59ca [IR] Switch everything to use memory attribute
This switches everything to use the memory attribute proposed in
https://discourse.llvm.org/t/rfc-unify-memory-effect-attributes/65579.
The old argmemonly, inaccessiblememonly and inaccessiblemem_or_argmemonly
attributes are dropped. The readnone, readonly and writeonly attributes
are restricted to parameters only.

The old attributes are auto-upgraded both in bitcode and IR.
The bitcode upgrade is a policy requirement that has to be retained
indefinitely. The IR upgrade is mainly there so it's not necessary
to update all tests using memory attributes in this patch, which
is already large enough. We could drop that part after migrating
tests, or retain it longer term, to make it easier to import IR
from older LLVM versions.

High-level Function/CallBase APIs like doesNotAccessMemory() or
setDoesNotAccessMemory() are mapped transparently to the memory
attribute. Code that directly manipulates attributes (e.g. via
AttributeList) on the other hand needs to switch to working with
the memory attribute instead.

Differential Revision: https://reviews.llvm.org/D135780
2022-11-04 10:21:38 +01:00
Matt Arsenault
5201680249 LangRef: Fix typo in backtick placement 2022-11-02 17:40:33 -07:00
Matt Arsenault
da137e114e LangRef: Attempt to formulate some rules for addrspacecast
Some work will be needed to comply with these rules for non-integral
pointers.
2022-11-01 18:46:18 -07:00
Yeting Kuo
71e4e35581 [VP][RISCV] Add vp.rint and RISC-V support.
FRINT uses dynamic rounding mode instead of static rounding mode. The patch
rename VFCVT_X_F_VL to VFCVT_RM_X_F_VL for static rounding mode uses and added
new ISDNode VFCVT_X_F_VL directly selected to PseudoVFCVT_X_F_V.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D136662
2022-11-01 14:52:47 +08:00
Nikita Popov
9d9de5a5df [LangRef] Add memory attribute
This adds the LangRef wording for the memory attribute proposed at
https://discourse.llvm.org/t/rfc-unify-memory-effect-attributes/65579.

The old attributes are not removed from LangRef until the migration
is finished.

Differential Revision: https://reviews.llvm.org/D135597
2022-10-21 12:11:25 +02:00
Kevin P. Neal
1b06307aa4 [LangRef][FMF] Clarify ambiguity.
This should eliminate some ambiguous grammer that tripped me up when
reviewing D136097.
2022-10-18 10:57:12 -04:00
Peter Rong
c2e7c9cb33 [CodeGen] Using ZExt for extractelement indices.
In https://github.com/llvm/llvm-project/issues/57452, we found that IRTranslator is translating `i1 true` into `i32 -1`.
This is because IRTranslator uses SExt for indices.

In this fix, we change the expected behavior of extractelement's index, moving from SExt to ZExt.
This change includes both documentation, SelectionDAG and IRTranslator.
We also included a test for AMDGPU, updated tests for AArch64, Mips, PowerPC, RISCV, VE, WebAssembly and X86

This patch fixes issue #57452.

Differential Revision: https://reviews.llvm.org/D132978
2022-10-15 15:45:35 -07:00
Craig Topper
9f67047cf0 [VP][RISCV] Add vp.smax/smin/umax/umin intrinsics
Differential Revision: https://reviews.llvm.org/D135418
2022-10-07 17:14:31 -07:00
eopXD
d9df1190cd [LangRef] Fix too short title underline 2022-10-07 02:24:56 -07:00
eopXD
dbc681c98e [VP][RISCV] Add vp.roundtozero and its RISC-V support
The scalar instruction of this is `llvm.trunc`. However the naming of
ISD::VP_TRUNC is already taken by `trunc` of the LLVM IR. Naming this as
`vp.ftrunc` would likely cause confusion with `vp.fptrunc`. So adding
`vp.roundtozero` that will look similar to `vp.roundeven`.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D135233
2022-10-07 02:15:23 -07:00
Fraser Cormack
043a585b05 [LangRef][VP] Change masked-off lanes from undef to poison
These were all changed in 32b1b06b7081bd722750c6f3d528336f3f7ed34b (as
discussed in D133967) but some intrinsics introduced since have
re-introduced `undef` as the masked-off value.

Reviewed By: reames, eopXD

Differential Revision: https://reviews.llvm.org/D135244
2022-10-05 15:24:14 +01:00
Yeting Kuo
cefb7aab61 [VP][RISCV] Add vp.copysign and RISC-V support.
Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D134935
2022-10-01 10:19:10 +08:00
Phoebe Wang
e150086652 [Doc] Fix typo. NFC
Fixes #56429
2022-09-30 14:00:42 +08:00
Ben Dunbobbin
7eee2a2d44 [IR] Don't allow DLL storage-class and local linkage
Disallow this meaningless combination. Doing so simplifies analysis
of LLVM code w.r.t t DLL storage-class, and prevents mistakes with
DLL storage class.

- Change the assembler to reject DLL storage class on symbols with
  local linkage.
- Change the bitcode reader to clear the DLL Storage class when the
  linkage is local for auto-upgrading
- Update LangRef.

There is an existing restriction on non-default visibility and local
linkage which this is modelled on.

Differential Review: https://reviews.llvm.org/D134784
2022-09-30 00:26:01 +01:00
eopXD
eb53416d0f [LangRef][Doc] Fix warning for too short title underline 2022-09-27 19:53:28 -07:00
eopXD
9677d70eb2 [VP][RISCV] Add vp.floor, vp.round, vp.roundeven and their RISC-V support
Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D134759
2022-09-27 19:45:58 -07:00
eopXD
163cb33854 [VP][RISCV] Add vp.ceil and RISC-V support
Previous commit 8b00b24f8505 missed to add `int_ceil` anchor for the
llvm.ceil.* section under LangRef.rst

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D134586
2022-09-27 12:04:09 -07:00
eopXD
384b8b3da7 Revert "[VP][RISCV] Add vp.ceil and RISC-V support"
This reverts commit 8b00b24f8505970f54eab85aad8db5845a635850.
2022-09-27 11:12:57 -07:00
eopXD
8b00b24f85 [VP][RISCV] Add vp.ceil and RISC-V support
Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D134586
2022-09-27 11:08:27 -07:00
Craig Topper
a6383bb51c [VP][RISCV] Add vp.fmuladd.
Expanded in SelectionDAGBuilder similar to llvm.fmuladd.

Reviewed By: frasercrmck, simoll

Differential Revision: https://reviews.llvm.org/D134474
2022-09-27 10:02:37 -07:00
Yeting Kuo
04e1301f3d [VP][RISCV] Add vp.maxnum and vp.minnum intrinsics and RISC-V support.
Add vp.maxnum and vp.minnum which are vector predicted intrinsics of llvm.maxnum
and llvm.minnum.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D134639
2022-09-27 13:36:45 +08:00
Yeting Kuo
43c5fbdd3a [VP][RISCV] Add vp.sqrt intrinsic and RISC-V support.
The patch modeled vp.fabs patch D132793.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D133690
2022-09-26 10:47:40 +08:00
J. Ryan Stinnett
74f0e64bb9 [LangRef][Docs] Fix RST header length for GC intrinsics
This fixes up the header length which regressed in
8c1a9e3cf37cb2aa6e67934e56796284efa42806.
2022-09-21 16:53:55 +01:00
J. Ryan Stinnett
8c1a9e3cf3 [LangRef][Docs] Align RST syntax for GC intrinsics
This changes the GC intrinsics to use the same header styling as the others.
2022-09-21 16:46:33 +01:00
Craig Topper
e6f8a6b56e [LangRef] Clarify that noimplicitfloat disables all implicit vectors not just floating point.
Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D134086
2022-09-19 10:13:51 -07:00