3 Commits

Author	SHA1	Message	Date
Xiaodong Liu	8d798eab16	[LoongArch] Add "32bit" target feature ... There are a few intrinsics or instructions on LoongArch that are only appropriate for loongarch32 target. So the feature "32bit" is added to implement it. Reviewed By: SixWeining Differential Revision: https://reviews.llvm.org/D140872	2023-01-06 09:28:55 +08:00
WANG Xuerui	ad6fe32032	[LoongArch] Support 'generic' as a valid CPU name ... As the LoongArch port is largely modeled after RISCV it has the same behavior of not accepting `generic` as a CPU name. For better compatibility with consumers of LLVM (e.g. mesa) follow D121149's suit and treat `generic` the same as an empty CPU name. Differential Revision: https://reviews.llvm.org/D134412	2022-09-26 10:20:13 +08:00
Lu Weining	33388ae866	[LoongArch 4/6] Add basic tablegen infra for LoongArch ... This patch introduces basic tablegen infra such as LoongArch{InstrFormats,InstrInfo,RegisterInfo,CallingConv,}.td. For now, only add instruction definitions for LoongArch basic integer operations. Our initial target is a working MC layer rather than codegen, so appropriate SelectionDAG patterns will come later. Differential revision: https://reviews.llvm.org/D115861	2022-02-10 10:23:34 +00:00