10 Commits

Author SHA1 Message Date
Lei Huang
7a7e9109a2 [PowerPC] Implement P10 Byte Reverse Insructions
Generate brh, brw and brd instructions for byte-swap operations
on P10 and generating a single instruction for a 32-bit swap followed
by a 16-bit right shift.

Reviewed By: stefanp

Differential Revision: https://reviews.llvm.org/D140414
2022-12-21 09:15:57 -06:00
Maryam Moghadas
c19f905fed [PowerPC] Implement xscmpeqqp, xscmpgeqp, xscmpgtqp instructions
This patch adds 3 Power10 VSX Scalar compare for quad precision
instructions including xscmpeqqp, xscmpgeqp, xscmpgtqp

Reviewed By: amyk

Differential Revision: https://reviews.llvm.org/D138592
2022-12-01 15:01:49 -06:00
Stefan Pintilie
1492c88f49 [PowerPC] Fix bugs in sign-/zero-extension elimination
This patch fixes the following two bugs in `PPCInstrInfo::isSignOrZeroExtended` helper, which is used from sign-/zero-extension elimination in PPCMIPeephole pass.
- Registers defined by load with update (e.g. LBZU) were identified as already sign or zero-extended. But it is true only for the first def (loaded value) and not for the second def (i.e. updated pointer).
- Registers defined by ORIS/XORIS were identified as already sign-extended. But, it is not true for sign extension depending on the immediate (while it is ok for zero extension).

To handle the first case, the parameter for the helpers is changed from `MachineInstr` to a register number to distinguish first and second defs. Also, this patch moves the initialization of PPCMIPeepholePass to allow mir test case.

Reviewed By: nemanjai

Differential Revision: https://reviews.llvm.org/D40554
2022-08-19 07:05:40 -05:00
Ting Wang
12e1936f64 [PowerPC] Add XXEVAL TD pattern
Add xxeval TD pattern for P10 on: eqv, nor, or, xor.

Reviewed By: shchenz

Differential Revision: https://reviews.llvm.org/D131654
2022-08-12 01:27:24 -04:00
Stefan Pintilie
ef34442232 [NFC][PowerPC] Move the Regsiter Operands for PowerPC into PPCRegisterInfo.td
Currently the regsiter operand definitions are found in three separate files.
This patch moves all of the definitions into PPCRegisterInfo.td.

Reviewed By: amyk

Differential Revision: https://reviews.llvm.org/D123543
2022-04-18 14:50:24 -05:00
Stefan Pintilie
bc9916fff2 [NFC][PowerPC] Style and ordering changes for PPCInstrP10.td
Renamed the two classes 8LS_DForm_R_SI34_RTA5 and 8LS_DForm_R_SI34_XT6_RA5 to
8LS_DForm_R_SI34_RTA5_MEM and 8LS_DForm_R_SI34_XT6_RA5_MEM because the
instructions that use the classes use memory reads/writes.

Moved the instruction defs up closer to the classes.
Removed unnecessary whitespace.
2022-04-18 13:28:48 -05:00
Stefan Pintilie
0625aed2fc [PowerPC][NFC] Split out the MMA instructions from the P10 instructions.
Currently all of the MMA instructions as well as the MMA related register info
is bundled with the Power 10 instructions. This patch just splits them out.

Reviewed By: lei

Differential Revision: https://reviews.llvm.org/D120515
2022-02-25 11:41:09 -06:00
Stefan Pintilie
4fbe60fd13 [PowerPC][NFC] Add file info and license that was missing from this file.
Added the license info as well as description about how classes should be named
based on existing documentation.

Reviewed By: lei, #powerpc

Differential Revision: https://reviews.llvm.org/D120530
2022-02-25 10:28:02 -06:00
Stefan Pintilie
eb1c5a9862 [PowerPC] Add the Power10 LXVKQ instrution.
Add the Power 10 instruction LXVKQ.

This patch was taken from an original patch by: Yi-Hong Lyu

Reviewed By: lei

Differential Revision: https://reviews.llvm.org/D117507
2022-02-23 08:48:59 -06:00
Lei Huang
5abe6c312b [PowerPC] Rename PPCInstrPrefix.td to PPCInstrP10.td 2022-02-16 10:22:41 -06:00