If we have `and x, (csel 0, 1, cc)` and we know that x is 0/1, then we
can emit a `csel ZR, x, cc`. Similarly for `or x, (csel 0, 1, cc)` we
can emit `csinc x, ZR, cc`. This can help where we can not otherwise
general ccmp instructions.
Differential Revision: https://reviews.llvm.org/D141119
* For case bcmp9, there is extras AND and EXTEND int the chain of OR/XOR,
which prevent the transform, so enable the optimize before legalization.
* The key IR frag related:
t37: i32,ch = load<(load (s8) from %ir.4), anyext from i8> t0, t11, undef:i64
t12: i64 = add t4, Constant:i64<8>
t38: i32,ch = load<(load (s8) from %ir.5), anyext from i8> t0, t12, undef:i64
t39: i32 = xor t37, t38
t40: i64 = any_extend t39
t42: i64 = and t40, Constant:i64<255>
Depends on D138398 to fix combine_setcc_glue
Reviewed By: dmgreen, bcl5980
Differential Revision: https://reviews.llvm.org/D137936
We already surpport the or (xor a, b), (xor c, d) with D136244, while it should
capture more cases than just bcmp according the comment on
https://reviews.llvm.org/D136672, so this patch try to fold continuous
comparison series.
Also add a new callsite in LowerSETCC to address some cases folded And in the
stage of `Optimized type-legalized selection`.
Depends on D136244
Reviewed By: dmgreen, bcl5980
Differential Revision: https://reviews.llvm.org/D137721
