3 Commits

Author SHA1 Message Date
Tim Northover
1ddc6ab1a9 AArch64: support ISel for fence instructions
Only the most conservative of the DAG patterns matched, leaving GISel with "dmb
ish" everywhere which is inefficient.
2022-05-16 12:01:18 +01:00
Konstantin Zhuravlyov
bb80d3e1d3 Enhance synchscope representation
OpenCL 2.0 introduces the notion of memory scopes in atomic operations to
  global and local memory. These scopes restrict how synchronization is
  achieved, which can result in improved performance.

  This change extends existing notion of synchronization scopes in LLVM to
  support arbitrary scopes expressed as target-specific strings, in addition to
  the already defined scopes (single thread, system).

  The LLVM IR and MIR syntax for expressing synchronization scopes has changed
  to use *syncscope("<scope>")*, where <scope> can be "singlethread" (this
  replaces *singlethread* keyword), or a target-specific name. As before, if
  the scope is not specified, it defaults to CrossThread/System scope.

  Implementation details:
    - Mapping from synchronization scope name/string to synchronization scope id
      is stored in LLVM context;
    - CrossThread/System and SingleThread scopes are pre-defined to efficiently
      check for known scopes without comparing strings;
    - Synchronization scope names are stored in SYNC_SCOPE_NAMES_BLOCK in
      the bitcode.

Differential Revision: https://reviews.llvm.org/D21723

llvm-svn: 307722
2017-07-11 22:23:00 +00:00
Tim Northover
1efaa3a88f AArch64: add test for "fence singlethread"
Forgot a git add yesterday.

llvm-svn: 301037
2017-04-21 20:36:08 +00:00