6 Commits

Author SHA1 Message Date
Philip Reames
fc0efb7e78 [SDAG] Allow scalable vectors in ComputeNumSignBits (try 2)
I had reverted this before the holiday week because a problem was reported with a related change (D137140 - scalable vector known bits in DAG).  I had initially confused the two patches, and then decided to leave this reverted out an abundance of caution.  Now that we're through the holiday week, reapplying.

I also roled in fixes for several post commit review comments that hadn't landed with the original change.

Original commit message

This is a continuation of the series of patches adding lane wise support for scalable vectors in various knownbit-esq routines.

The basic idea here is that we track a single lane for scalable vectors which corresponds to an unknown number of lanes at runtime. This is enough for us to perform lane wise reasoning on many arithmetic operations.

Differential Revision: https://reviews.llvm.org/D137141
2022-11-29 08:25:05 -08:00
Philip Reames
102f05bd34 Revert "[SDAG] Allow scalable vectors in ComputeNumSignBits" and follow up
This reverts commits 3fb08d14a63f5f745d3fec2b5f6ffef4cf0a398c and f8c63a7fbf50fb5883bd566c7539d0ac18c7700f.

There was a "timeout for a Halide Hexagon test" reported.  Revert until investigation complete.
2022-11-18 15:25:59 -08:00
Philip Reames
f8c63a7fbf [SDAG] Allow scalable vectors in ComputeNumSignBits
This is a continuation of the series of patches adding lane wise support for scalable vectors in various knownbit-esq routines.

The basic idea here is that we track a single lane for scalable vectors which corresponds to an unknown number of lanes at runtime. This is enough for us to perform lane wise reasoning on many arithmetic operations.

Differential Revision: https://reviews.llvm.org/D137141
2022-11-18 10:50:06 -08:00
Paul Walker
bcda4c48c8 [SVE] By using SEL when orring predicates we forgo the need for a PTRUE.
Differential Revision: https://reviews.llvm.org/D118463
2022-01-31 19:39:23 +00:00
Fraser Cormack
e1acbda158 [AArch64][RISCV] Fix expected smulo/umulo test output
These tests were introduced in D109809 which I pushed on behalf of
@tangxingxin1008. I must have not understood the correct arcanist
workflow for this and as such may have locally tested a stale build.

This patch fixes the issue by re-running update_llc_test_checks.py on
all four tests.
2021-11-18 11:57:26 +00:00
Eric Tang
9fe6b9e802 [TargetLowering][RISCV] Fixed a scalable vector issue when lowering [s|u]mul.overflow intrinsics
Fixed the vector type issue that where we used getVectorNumElements()
    should be replaced by getVectorElementCount() when lowering these
    intrinsics.

    This is similar to D94149

Signed-off-by: Eric Tang <tangxingxin1008@gmail.com>

Reviewed By: craig.topper, frasercrmck

Differential Revision: https://reviews.llvm.org/D109809
2021-11-18 10:16:08 +00:00