6 Commits

Author SHA1 Message Date
Zi Xuan Wu (Zeson)
62c4dce5b4 [CSKY][NFC] Fix check-all error due to change of expected output
- Remove unnecessary symbol offset check in MC cases.
- Change other expected output in CodeGen cases.
2022-12-12 11:30:52 +08:00
Zi Xuan Wu (Zeson)
70b8b738c5 [CSKY] Fix the btsti16 instruction missing in generic processor
Normally, generic processor does not have any SubtargetFeature. And it
can just generate most basic instructions which have no Predicates to
guard.

But it needs to enbale predicate for the btsti16 instruction as one of the most basic instructions.
Or the generic processor can't finish codegen process. So Add FeatureBTST16 SubtargetFeature to generic ProcessorModel.
2022-07-27 17:39:15 +08:00
Zi Xuan Wu (Zeson)
08db089124 [CSKY] Fix the testcase error due to the verifyInstructionPredicates
- Test cases for arch only has 16-bit instruction such as ck801/ck802 need
compile with -mattr=+btst16
- Fix the GPR copy instruction with MOV16 for 16-bit only arch.
2022-07-21 15:53:50 +08:00
Zi Xuan Wu
208f93c1fd [CSKY] support select instruction in floating type
In FPUv3, there is fsel.32/64 instruction to select float/double type data.
In FPUv2, split block and use branch and move instruction to select float/double type data.
2022-04-08 12:38:50 +08:00
Zi Xuan Wu
cfcac264e2 [CSKY] Support bitcast operation from/to double to/from two GPRs
In soft ABI, floating num is passing in GPRs. So we need support
bitcovert from double to Hi and Lo GPRs and vice versa
2022-04-07 18:36:04 +08:00
Zi Xuan Wu
4ad517e6b0 [CSKY] Add floating operation support including float and double
CSKY arch has multiple FPU instruction versions such as FPU, FPUv2 and FPUv3 to implement floating operations.
For now, we just only support FPUv2 and FPUv3.

It includes the encoding, asm parsing of instructions and codegen of DAG nodes.
2022-01-27 15:54:04 +08:00