3 Commits

Author SHA1 Message Date
Yeting Kuo
e2b65ff98d [RISCV] Use tail agnostic if inserting subvector/element at the end of a vector.
The patch tries to make more vslidup nodes use tail agnostic. The idea comes
from D125546 authored by Zack Chen.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D140669
2022-12-31 11:29:09 +08:00
Philip Reames
d89d45ca9a [RISCV][InsertVSETVLI] Default to MA not MU
This changes the default value used for mask policy from mask undisturbed to mask agnostic. In hardware, there may be a minor preference for ta/ma, but since this is only going to apply to instructions which don't use the mask policy bit, this is functionally mostly a nop. The main value is to make future changes to using MA when legal for masked instructions easier to review by reducing test churn.

The prior code was motivated by a desire to minimize state transitions between masked and unmasked code. This patch achieves the same effect using the demanded field logic (landed in afb45ff), and there are no regressions I spotted in the test diffs. (Given the size, I have only been able to skim.) I do want to call out that regressions are possible here; the demanded analysis only works on a block local scope right now, so e.g. a tight loop mixing masked and unmasked computation might see an extra vsetvli or two.

Differential Revision: https://reviews.llvm.org/D133803
2022-10-06 07:59:39 -07:00
liqinweng
0516ad8706 [RISCV] Add and update reverse mask tests, NFC
Reviewed By: Jimerlife

 Differential Revision: https://reviews.llvm.org/D134520
2022-09-28 18:44:46 +08:00