2 Commits

Author	SHA1	Message	Date
Kazushi (Jam) Marukawa	44a679eaa4	[VE] Change the behaviour of truncate ... Change the way to truncate i64 to i32 in I64 registers. VE assumed sext values previously. Change it to zext values this time to make it match to the LLVM behaviour. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D92226	2020-11-30 22:12:45 +09:00
Simon Moll	ffe6c97f6b	[VE] VEC_BROADCAST, lowering and isel ... This defines the vec_broadcast SDNode along with lowering and isel code. We also remove unused type mappings for the vector register classes (all vector MVTs that are not used in the ISA go). We will implement support for short vectors later by intercepting nodes with illegal vector EVTs before LLVM has had a chance to widen them. Reviewed By: kaz7 Differential Revision: https://reviews.llvm.org/D91646	2020-11-19 09:44:56 +01:00