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330 Commits

Author SHA1 Message Date
Dmitry Preobrazhensky
e7a306310b [AMDGPU][GFX11] Correct tied src2 of v_fmac_f16_e64 
src2 was incorrectly defined as VSrc_f16 but it is tied to dst which is VGPR_32. As a result, disassembler failed to decode src2.

Differential Revision: https://reviews.llvm.org/D140299
 2022-12-30 16:42:15 +03:00
Dmitry Preobrazhensky
9f40d9ffd1 [AMDGPU][MC][GFX11] Correct encoding of neg modifier for v_dot2_f32_bf16 
Fix a bug with neg_lo:[0,1,0] and neg_hi:[0,1,0] modifiers - they are accepted but not encoded.

Differential Revision: https://reviews.llvm.org/D140470
 2022-12-30 16:25:22 +03:00
Petar Avramovic
cc6b10d1ee AMDGPU: Check if operand RC contains register used when printing 
Disassembler can successfully decode sgpr register when only vgpr
registers are valid for the operand (e.g. VReg_* and VISrc_* operands).
In InstPrinter, detect when operand register class does not contain
register that is being printed. Does not result in an error.
Intended use is for disassembler tests.

Differential Revision: https://reviews.llvm.org/D139646
 2022-12-09 17:55:57 +01:00
Petar Avramovic
a1ceacd050 AMDGPU: Precommit wmma tests for D139646 2022-12-09 17:55:56 +01:00
Joe Nash
bbfbec94b1 [AMDGPU] Enable OMod on more VOP3 instructions 
OMod was disabled if OpSel was enabled, but that restriction is more
specific than necessary. Any VOP3 with float operands can use OMod.

On GFX11, FMAC_F16_e64 can use op_sel.
Previously, SIFoldOperands and convertToThreeAddress were accidentally correct when
they reinterpreted the zero OMod operand on V_FMAC_F16_e64 as the OpSel operand on
V_FMA_F16_gfx9_e64. Now we explicitly add op_sel if required.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D139469
 2022-12-07 13:30:33 -05:00
Jay Foad
b9f3977b26 [AMDGPU] Add MC tests for s_endpgm's optional immediate operand 
Differential Revision: https://reviews.llvm.org/D139438
 2022-12-06 17:04:50 +00:00
Jay Foad
c634e1a28a [AMDGPU] Remove FIXME that was addressed by D99413 2022-12-06 14:50:47 +00:00
Mateja Marjanovic
595a08847a [AMDGPU] Add support for new LLVM vector types 
Add VReg, AReg and SReg on AMDGPU for bit widths: 288, 320, 352 and 384.

Differential Revision: https://reviews.llvm.org/D138205
 2022-11-29 17:02:04 +01:00
Dmitry Preobrazhensky
9b8eb5fa8e [AMDGPU][MC][GFX11] Correct op_sel handling for permlane*16 
Differential Revision: https://reviews.llvm.org/D137969
 2022-11-29 18:45:22 +03:00
Dmitry Preobrazhensky
869fc7eabd [AMDGPU][MC][MI100+] Enable VOP3 variants of dot2c/dot4c/dot8c opcodes 
Differential Revision: https://reviews.llvm.org/D138494
 2022-11-29 17:38:18 +03:00
Piotr Sobczak
de767db633 [AMDGPU] Add encoding tests for SALU_CYCLE_2/3 
Add missing assembler/disassembler tests for INSTID_SALU_CYCLE_2
and INSTID_SALU_CYCLE_3 which are possible arguments in S_DELAY_ALU.

Differential Revision: https://reviews.llvm.org/D138482
 2022-11-22 11:41:59 +01:00
Joe Nash
38f47d90db [AMDGPU][MC][NFC] Rename VOP3 VOPC test files 
D136149 and D136148 renamed the MC test files for VOP3 promoted from VOP1 and
VOP2 in a consistent way. Do the same for VOP3 coming from VOPC.

Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D137950
 2022-11-14 13:27:38 -05:00
Dmitry Preobrazhensky
6e279f5bb6 [AMDGPU][MC][GFX10+] Enable literal operands with permlane16/permlanex16 
Differential Revision: https://reviews.llvm.org/D137332
 2022-11-07 15:49:21 +03:00
Mirko Brkusanin
093200fd00 [AMDGPU][NFC] Split MC tests into promoted from VOP1 to VOP3 and only VOP3 
Differential Revision: https://reviews.llvm.org/D136149
 2022-11-02 12:30:23 +01:00
Mirko Brkusanin
7e1963b191 [AMDGPU][NFC] Split MC tests into promoted from VOP2 to VOP3 and only VOP3 
Differential Revision: https://reviews.llvm.org/D136148
 2022-11-02 12:30:23 +01:00
Dmitry Preobrazhensky
bf96703fb3 [AMDGPU][MC][GFX8+] Correct v_cndmask modifiers 
Correct v_cndmask_b32 to support abs/neg modifiers in dpp/sdwa/e64 variants.
Correct v_cndmask_b16 for proper disassembly of abs/neg modifiers in e64_dpp variants.

Differential Revision: https://reviews.llvm.org/D135900
 2022-10-14 19:37:27 +03:00
Dmitry Preobrazhensky
4e62d02db9 [AMDGPU][MC] Correct image_gather4h 
Correct encoding of image_gather4h for GFX9; disable this instruction for SI, CI and VI.

Differential Revision: https://reviews.llvm.org/D135605
 2022-10-11 14:41:27 +03:00
Dmitry Preobrazhensky
8f8e4e3b38 [AMDGPU][MC][GFX11] Correct v_fmac_.*_e64_dpp 
Differential Revision: https://reviews.llvm.org/D134961
 2022-10-07 16:21:55 +03:00
Joe Nash
203d0b0ee1 [AMDGPU] Fix V_CMP_CLASS_F16_t16_e64 src1 type. 
For V_CMP_CLASS_F16_t16_e64 and V_CMPX_CLASS_F16_t16_e64,
https://reviews.llvm.org/D133723 changed the value type of src1 from i32 to i16.
These src1 operands are 16 bits, therefore need to be encoded as true16
operands. So the _e32 type was correctly set to VGPR_32_Lo128.
In _e64 form the operand class went from
VSrc_b32 to VSrc_b16. For some reason, we cannot encode inline literals for
VSrc_b16, see 5f5f566b265db00f577ead268400d99f34ba9cdd. In this phase of
the true16 implementation, VSrc_b16 and VSrc_b32 are still similar,
except from that quirk of inlines. So set the operand class to regain
that function.

Reviewed By: dp, arsenm

Differential Revision: https://reviews.llvm.org/D134897
 2022-10-05 11:15:40 -04:00
Dmitry Preobrazhensky
f4b1cfa1cb [AMDGPU][MC][GFX11] Correct e64_dpp variants of v_movreld and v_movrelsd 
Differential Revision: https://reviews.llvm.org/D135079
 2022-10-05 16:47:18 +03:00
Dmitry Preobrazhensky
485c539391 [AMDGPU][MC][GFX11] Disable non-null src0 for s_waitcnt_*cnt 
Differential Revision: https://reviews.llvm.org/D134809
 2022-09-29 19:56:03 +03:00
Jay Foad
3822a01e0b [AMDGPU] Add GFX11 ds_bvh_stack_rtn_b32 instruction 
Differential Revision: https://reviews.llvm.org/D133928
 2022-09-15 16:46:14 +01:00
Dmitry Preobrazhensky
405b19bb67 [AMDGPU][MC][GFX11] Add disassembler tests for v_readfirstlane_b32 
Differential Revision: https://reviews.llvm.org/D133437
 2022-09-15 18:18:33 +03:00
Dmitry Preobrazhensky
b0eea8f440 [AMDGPU][MC][GFX11][NFC] Update disassembler tests for MIMG instructions 
Differential Revision: https://reviews.llvm.org/D133411
 2022-09-15 18:04:34 +03:00
Dmitry Preobrazhensky
6d63a531e2 [AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOPD instructions 
Differential Revision: https://reviews.llvm.org/D133414
 2022-09-09 13:10:55 +03:00
Dmitry Preobrazhensky
c07ea46f21 [AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOP3P instructions 
Differential Revision: https://reviews.llvm.org/D133412
 2022-09-09 13:06:44 +03:00
Dmitry Preobrazhensky
efa65ef281 [AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOP3 instructions 
Differential Revision: https://reviews.llvm.org/D133350
 2022-09-07 13:55:27 +03:00
Dmitry Preobrazhensky
a95b45d380 [AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOP3.DPP8 instructions 
Differential Revision: https://reviews.llvm.org/D133353
 2022-09-07 13:51:31 +03:00
Dmitry Preobrazhensky
c777c8f022 [AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOP3.DPP16 instructions 
Differential Revision: https://reviews.llvm.org/D133356
 2022-09-07 13:47:55 +03:00
Dmitry Preobrazhensky
67d148b63c [AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOPC and VOPC.DPP instructions 
Differential Revision: https://reviews.llvm.org/D132737
 2022-08-26 21:38:55 +03:00
Dmitry Preobrazhensky
35e2107842 [AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOP2 and VOP2.DPP instructions 
Differential Revision: https://reviews.llvm.org/D132733
 2022-08-26 21:32:55 +03:00
Dmitry Preobrazhensky
ad39f1fa8c [AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOP1 and VOP1.DPP instructions 
Differential Revision: https://reviews.llvm.org/D132731
 2022-08-26 21:30:08 +03:00
Dmitry Preobrazhensky
8ff3cea076 [AMDGPU][MC][GFX11][NFC] Add missing tests for SOP instructions 
Differential Revision: https://reviews.llvm.org/D132404
 2022-08-24 13:45:20 +03:00
Dmitry Preobrazhensky
5e7d43ffef [AMDGPU][MC][GFX11][NFC] Update tests for FLAT instructions 
Differential Revision: https://reviews.llvm.org/D132402
 2022-08-24 13:38:09 +03:00
Dmitry Preobrazhensky
badf8aed30 [AMDGPU][MC][NFC] Rename disassembler tests 
Make test names more uniform.

Differential Revision: https://reviews.llvm.org/D132472
 2022-08-24 13:26:57 +03:00
Dmitry Preobrazhensky
8f3c160b8b [AMDGPU][MC][GFX8][NFC] Consolidate tests by encoding 
Differential Revision: https://reviews.llvm.org/D132469
 2022-08-24 13:13:22 +03:00
Dmitry Preobrazhensky
4b9016da0a [AMDGPU][MC][GFX9][NFC] Consolidate tests by encoding 
Differential Revision: https://reviews.llvm.org/D132409
 2022-08-23 13:13:36 +03:00
Dmitry Preobrazhensky
0a8dd8ef79 [AMDGPU][MC][GFX10][NFC] Consolidate tests by encoding 
Differential Revision: https://reviews.llvm.org/D132235
 2022-08-22 19:53:56 +03:00
Dmitry Preobrazhensky
e99f6df726 [AMDGPU][MC][GFX9][NFC] Split large test file 
Split gfx9_dasm_all.txt by instruction encoding.

Differential Revision: https://reviews.llvm.org/D132124
 2022-08-19 14:01:42 +03:00
Dmitry Preobrazhensky
bdb859c9a7 [AMDGPU][MC][GFX8][NFC] Split large test file 
Split gfx8_dasm_all.txt by instruction encoding.

Differential Revision: https://reviews.llvm.org/D132126
 2022-08-19 13:54:56 +03:00
Dmitry Preobrazhensky
7e29d5c04b [AMDGPU][MC][GFX10][NFC] Split large test 
Split gfx10_dasm_all.txt by encoding.

Differential Revision: https://reviews.llvm.org/D132044
 2022-08-18 12:39:34 +03:00
Dmitry Preobrazhensky
4e68834add [AMDGPU][MC][GFX11][NFC] Add tests for VOP1 and VOP2 16 bit opcodes 
Differential Revision: https://reviews.llvm.org/D131588
 2022-08-11 17:12:13 +03:00
Dmitry Preobrazhensky
eda6e49aa8 [AMDGPU][MC][GFX11][NFC] Correct tests for 16-bit VOP2 opcodes which use v128 or higher VGPRs 
Differential Revision: https://reviews.llvm.org/D131564
 2022-08-11 15:55:58 +03:00
Dmitry Preobrazhensky
9d1eeefbfe [AMDGPU][MC][GFX11][NFC] Rename tests 
Make test names more uniform.

Differential Revision: https://reviews.llvm.org/D131398
 2022-08-09 13:56:05 +03:00
Dmitry Preobrazhensky
fc4c1a86f3 [AMDGPU][MC][GFX11][NFC] Split large tests 
Differential Revision: https://reviews.llvm.org/D131397
 2022-08-09 13:24:23 +03:00
Dmitry Preobrazhensky
05b3aadfff [AMDGPU][MC][GFX11] Correct v_dot2_f16_f16 and v_dot2_bf16_bf16 
Enable SGPRs for the following operands of these opcodes:

- src operands of VOP3 variant.
- src2 operand of DPP variants.

Differential Revision: https://reviews.llvm.org/D130989
 2022-08-03 15:08:23 +03:00
Dmitry Preobrazhensky
ae553f9e49 [AMDGPU][MC][GFX10] Correct encoding of VOP3 v_cmpx* opcodes 
Encode dst=EXEC but allow disassembler accept any dst value.

Differential Revision: https://reviews.llvm.org/D130978
 2022-08-03 15:03:44 +03:00
Dmitry Preobrazhensky
bb901dcc5a [AMDGPU][MC][GFX940] Correct disassembly of MFMA opcodes 
Add a decoder table for GFX940 MFMA opcodes.

Differential Revision: https://reviews.llvm.org/D130759
 2022-08-01 16:00:47 +03:00
Petar Avramovic
e8d260753e [AMDGPU] gfx11 allow dlc for MUBUF atomics 
Add MC support for dlc in gfx11 MUBUF atomic instructions.

Differential Revision: https://reviews.llvm.org/D129075
 2022-08-01 12:18:01 +02:00
Mirko Brkusanin
6a1aa627fa [AMDGPU] Enable image_gather4h instruction for gfx10 and gfx11 
Differential Revision: https://reviews.llvm.org/D130764
 2022-07-29 15:42:06 +02:00