500 Commits

Author SHA1 Message Date
Ivan Kosarev
a3a8cbffcf [AMDGPU][AsmParser][NFC] Refine parsing of NamedOperandU32 operands.
Eliminates the need for the custom code in parseCustomOperand().

Part of <https://github.com/llvm/llvm-project/issues/62629>.

Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D150980
2023-05-29 17:01:44 +01:00
Ivan Kosarev
212af2c081 [AMDGPU][AsmParser] Refine parsing of some 32-bit instruction operands.
Eliminates the need for the custom code in parseCustomOperand().

The remaining uses of NamedOperandU32 are to be addressed separately.

Part of <https://github.com/llvm/llvm-project/issues/62629>.

Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D150204
2023-05-19 16:54:30 +01:00
Diana Picus
bcbd9b021a [AMDGPU][MC] Don't accept attr > 32 for param_load
The docs say the interpolation attribute should be between 0..32 [1][2],
but we currently accept values all the way up to 63.

This patch makes the ASMParser error out for values > 32. It does not
touch codegen though because we're currently not checking anything at
all for codegen (llvm.amdgcn.lds.param.load will happily accept even 128
as an attr, although that won't fit in the encoding).

[1] https://llvm.org/docs/AMDGPU/gfx8_attr.html#amdgpu-synid-gfx8-attr
[2] https://llvm.org/docs/AMDGPU/gfx11_attr.html#amdgpu-synid-gfx11-attr

Differential Revision: https://reviews.llvm.org/D150261
2023-05-15 08:32:11 +02:00
Diana Picus
7591a7b6ea [AMDGPU][MC] Clean up DPP bound_ctrl handling
At the moment, we set the BC bit in DPP for both bound_ctrl:0 and
bound_ctrl:1, for compatibility with sp3 (see PR35397). However, this
hack is only needed for GFX8. For newer GFXs, sp3 behaves as expected,
i.e. it sets the bit when bound_ctrl:1 and clears it when bound_ctrl:0.

This patch updates LLVM to do the same for GFX11 or newer. We preserve
the current behaviour for GFX9 and 10 so we don't break any existing
code.

Differential Revision: https://reviews.llvm.org/D149254
2023-05-10 11:40:53 +02:00
NAKAMURA Takumi
c1221251fb Restore CodeGen/MachineValueType.h from Support
This is rework of;

  - rG13e77db2df94 (r328395; MVT)

Since `LowLevelType.h` has been restored to `CodeGen`, `MachinveValueType.h`
can be restored as well.

Depends on D148767

Differential Revision: https://reviews.llvm.org/D149024
2023-05-03 00:13:20 +09:00
Jay Foad
735cb7b1f8 [AMDGPU] Avoid using tuple where pair does suffice
Fixes the following building errors, happening with official Android prebuilt clang 14 shipped with Android 13:

external/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp:5491:13: error: no viable constructor or deduction guide for deduction of template arguments of 'tuple'
          ? std::tuple(HSAMD::V3::AssemblerDirectiveBegin,
            ^
...
external/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp:5493:13: error: no viable constructor or deduction guide for deduction of template arguments of 'tuple'
          : std::tuple(HSAMD::AssemblerDirectiveBegin,
            ^

Fixes: 6443c0e ("[AMDGPU] Stop using make_pair and make_tuple. NFC.")

Patch by Mauro Rossi!

Differential Revision: https://reviews.llvm.org/D142839
2023-04-21 08:30:35 +01:00
Ivan Kosarev
32f6b6bff5 [AMDGPU][AsmParser] Refine parsing SDWA operands.
Removes the need for the custom code in parseCustomOperand().

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D147241
2023-04-18 15:26:15 +01:00
Ivan Kosarev
5114843983 [AMDGPU][AsmParser] Refine SMRD offset definitions.
- Fixes the type of default 8-bit offset operands.
- Adds a test for optional offsets.

This is effectively an NFC.

Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D142231
2023-03-30 15:29:41 +01:00
Kazu Hirata
7ada7bbee1 [Target] Use *{Set,Map}::contains (NFC) 2023-03-14 18:06:55 -07:00
Jay Foad
dc3882eace [AMDGPU] Fix .amdhsa_shared_vgpr_count error checking for GFX11
Differential Revision: https://reviews.llvm.org/D145936
2023-03-14 09:05:32 +00:00
Ivan Kosarev
b06e5ad8a6 [AMDGPU][AsmParser][NFC] Simplify parsing cache policies.
Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D144954
2023-03-01 12:34:21 +00:00
Ivan Kosarev
905fa15d84 [AMDGPU][AsmParser] Distinguish literal and modifier SMEM offsets.
Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D144902
2023-02-28 12:58:54 +00:00
Mirko Brkusanin
b3dc0e69cf [AMDGPU][MC][GFX11] Add Partial NSA format for image sample instructions
Image sample instructions that need more than 5 VGPRs for VAddr can use
partial NSA for NSA encoding format. VGPRs that can not fit into the
encoding are sequential after the last one.
This patch adds assembly and disassembly parts.

Differential Revision: https://reviews.llvm.org/D144033
2023-02-23 13:33:34 +01:00
Changpeng Fang
7ca3444fba AMDGPU: Use module flag to get code object version at IR level folow-up
Summary:
  This is part of the leftover work for https://reviews.llvm.org/D143138.
In this work, we pass code object version as an argument to initialize target ID
and use it for targetID dump.

Reviewers: arsenm

Differential Revision
  https://reviews.llvm.org/D143293
2023-02-10 11:16:38 -08:00
Ivan Kosarev
f0f8ae7596 [AMDGPU][AsmParser] Fix matching immediate literals.
Prevents potential matching of literal offsets to non-literal operands.

Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D142194
2023-02-10 11:36:07 +00:00
Archibald Elliott
8e3d7cf5de [NFC][TargetParser] Remove llvm/Support/TargetParser.h 2023-02-07 11:08:21 +00:00
Changpeng Fang
54cf69c9d5 AMDGPU: Use module flag to get code object version at IR level
Summary:
  This patch introduces a mechanism to check the code object version from the module flag, This avoids checking from command line.
In case the module flag is missing, we use the current default code object version supported in the compiler.

For tools whose inputs are not IR, we may need other approach (directive, for example) to check the code
object version, That will be in a separate patch later.

For LIT tests update, we directly add module flag if there is only a single code object version associated with all checks in one file.
In cause of multiple code object version in one file, we use the "sed" method to "clone" the checks to achieve the goal.

Reviewer: arsenm

Differential Revision:
  https://reviews.llvm.org/D14313
2023-02-02 18:57:26 -08:00
Fangrui Song
7d3a181c8c [MC] Simplify code with parseComma 2023-02-01 18:41:02 -08:00
Jay Foad
073401e59c [MC] Define and use MCInstrDesc implicit_uses and implicit_defs. NFC.
The new methods return a range for easier iteration. Use them everywhere
instead of getImplicitUses, getNumImplicitUses, getImplicitDefs and
getNumImplicitDefs. A future patch will remove the old methods.

In some use cases the new methods are less efficient because they always
have to scan the whole uses/defs array to count its length, but that
will be fixed in a future patch by storing the number of implicit
uses/defs explicitly in MCInstrDesc. At that point there will be no need
to 0-terminate the arrays.

Differential Revision: https://reviews.llvm.org/D142215
2023-01-23 14:44:58 +00:00
Jay Foad
768aed1378 [MC] Make more use of MCInstrDesc::operands. NFC.
Change MCInstrDesc::operands to return an ArrayRef so we can easily use
it everywhere instead of the (IMHO ugly) opInfo_begin and opInfo_end.
A future patch will remove opInfo_begin and opInfo_end.

Also use it instead of raw access to the OpInfo pointer. A future patch
will remove this pointer.

Differential Revision: https://reviews.llvm.org/D142213
2023-01-23 11:31:41 +00:00
Kazu Hirata
caa99a01f5 Use llvm::popcount instead of llvm::countPopulation(NFC) 2023-01-22 12:48:51 -08:00
Ivan Kosarev
ce1aae4d54 [AMDGPU][AsmParser][NFC] Refine defining single-bit custom operands.
Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D141301
2023-01-16 16:11:59 +00:00
Ivan Kosarev
9976127605 [AMDGPU][AsmParser][NFC] Refine defining i8- and i16-typed custom operands.
Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D140799
2023-01-13 09:49:58 +00:00
Jay Foad
f460c66581 [AMDGPU] Simplify getNumFlatOffsetBits. NFC.
Previously we considered this field to be either N-bit unsigned or
N+1-bit signed, depending on the instruction. I think it's conceptually
simpler to say that the field is always N+1-bit signed, but some
instructions do not allow negative values.

Differential Revision: https://reviews.llvm.org/D140883
2023-01-12 10:40:36 +00:00
Ivan Kosarev
2d945ef864 [AMDGPU][NFC] Rename GFX10A16 operands.
They do not seem to be GFX10-specific anymore. Also renames the
corresponding feature.

Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D141069
2023-01-09 17:18:46 +00:00
serge-sans-paille
38818b60c5
Move from llvm::makeArrayRef to ArrayRef deduction guides - llvm/ part
Use deduction guides instead of helper functions.

The only non-automatic changes have been:

1. ArrayRef(some_uint8_pointer, 0) needs to be changed into ArrayRef(some_uint8_pointer, (size_t)0) to avoid an ambiguous call with ArrayRef((uint8_t*), (uint8_t*))
2. CVSymbol sym(makeArrayRef(symStorage)); needed to be rewritten as CVSymbol sym{ArrayRef(symStorage)}; otherwise the compiler is confused and thinks we have a (bad) function prototype. There was a few similar situation across the codebase.
3. ADL doesn't seem to work the same for deduction-guides and functions, so at some point the llvm namespace must be explicitly stated.
4. The "reference mode" of makeArrayRef(ArrayRef<T> &) that acts as no-op is not supported (a constructor cannot achieve that).

Per reviewers' comment, some useless makeArrayRef have been removed in the process.

This is a follow-up to https://reviews.llvm.org/D140896 that introduced
the deduction guides.

Differential Revision: https://reviews.llvm.org/D140955
2023-01-05 14:11:08 +01:00
Jay Foad
6f7ff9b933 [MC] Consistently use MCInstrDesc::getImplicitUses and getImplicitDefs. NFC. 2023-01-04 13:16:12 +00:00
Ivan Kosarev
0a6dc9a816 [AMDGPU][AsmParser] Refine parsing cache policy modifiers.
Reviewed By: dp, arsenm

Differential Revision: https://reviews.llvm.org/D140108
2022-12-30 15:44:34 +00:00
Sergei Barannikov
4d48ccfc88 [MC] Use MCRegister instead of unsigned in MCTargetAsmParser
Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D140273
2022-12-18 12:12:05 -08:00
Jay Foad
6443c0ee02 [AMDGPU] Stop using make_pair and make_tuple. NFC.
C++17 allows us to call constructors pair and tuple instead of helper
functions make_pair and make_tuple.

Differential Revision: https://reviews.llvm.org/D139828
2022-12-14 13:22:26 +00:00
Fangrui Song
67819a72c6 [CodeGen] llvm::Optional => std::optional 2022-12-13 09:06:36 +00:00
Petar Avramovic
cc6b10d1ee AMDGPU: Check if operand RC contains register used when printing
Disassembler can successfully decode sgpr register when only vgpr
registers are valid for the operand (e.g. VReg_* and VISrc_* operands).
In InstPrinter, detect when operand register class does not contain
register that is being printed. Does not result in an error.
Intended use is for disassembler tests.

Differential Revision: https://reviews.llvm.org/D139646
2022-12-09 17:55:57 +01:00
Dmitry Preobrazhensky
453eb9eb42 [AMDGPU][MC] Correct handling of mandatory literals
Differential Revision: https://reviews.llvm.org/D138661
2022-12-05 16:23:47 +03:00
Petar Avramovic
fc85ccd7b3 AMDGPU/MC: Simplify AsmParser for VOP3P
Remove check that instruction has src_modifiers because
isRegOrImmWithInputMods essentially includes this check.
isMod is no longer used after the refactor. Also, was unreachable case
inside for loop. clamp and omod operands are handled after the loop.

Differential Revision: https://reviews.llvm.org/D139194
2022-12-05 12:45:39 +01:00
Kazu Hirata
20cde15415 [Target] Use std::nullopt instead of None (NFC)
This patch mechanically replaces None with std::nullopt where the
compiler would warn if None were deprecated.  The intent is to reduce
the amount of manual work required in migrating from Optional to
std::optional.

This is part of an effort to migrate from llvm::Optional to
std::optional:

https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-02 20:36:06 -08:00
Mateja Marjanovic
595a08847a [AMDGPU] Add support for new LLVM vector types
Add VReg, AReg and SReg on AMDGPU for bit widths: 288, 320, 352 and 384.

Differential Revision: https://reviews.llvm.org/D138205
2022-11-29 17:02:04 +01:00
Dmitry Preobrazhensky
9b8eb5fa8e [AMDGPU][MC][GFX11] Correct op_sel handling for permlane*16
Differential Revision: https://reviews.llvm.org/D137969
2022-11-29 18:45:22 +03:00
Dmitry Preobrazhensky
869fc7eabd [AMDGPU][MC][MI100+] Enable VOP3 variants of dot2c/dot4c/dot8c opcodes
Differential Revision: https://reviews.llvm.org/D138494
2022-11-29 17:38:18 +03:00
Ivan Kosarev
536b8c5377 [AMDGPU][AsmParser] Remove the now-unused OptionalOperand structure.
Became unused in https://reviews.llvm.org/D138492 .
2022-11-28 11:00:05 +00:00
Kazu Hirata
96cb34ab5a [AsmParser] Use std::optional in AMDGPUAsmParser.cpp (NFC)
This is part of an effort to migrate from llvm::Optional to
std::optional:

https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-11-25 22:36:37 -08:00
Ivan Kosarev
fce7a7aa9f [AMDGPU][AsmParser] Refine parsing instruction operands.
Eliminates the need for working around optional and token operands being
mistakenly parsed as expressions.

Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D138492
2022-11-24 10:50:26 +00:00
Pierre van Houtryve
220147d536 [AMDGPU] Make aperture registers 64 bit
Makes the SRC_(SHARED|PRIVATE)_(BASE|LIMIT) registers 64 bit instead of 32.
They're still usable as 32 bit operands by using the _LO suffix.

Preparation for D137542

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D137767
2022-11-22 09:17:59 +00:00
Dmitry Preobrazhensky
96155bf44b [AMDGPU][GFX11][NFC] Refactor VOPD operands handling (part 2)
Rename interface functions and operands to make code clearer.

Differential Revision: https://reviews.llvm.org/D138133
2022-11-18 14:15:05 +03:00
Dmitry Preobrazhensky
e468b1b740 [AMDGPU][GFX11] Refactor VOPD operands handling
Differential Revision: https://reviews.llvm.org/D137952
2022-11-16 16:29:12 +03:00
Ivan Kosarev
d55594bb5e [AMDGPU][AsmParser] Forbid TFE modifiers for MBUF stores.
Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D137832
2022-11-14 16:10:36 +00:00
Ivan Kosarev
1b560e6ab7 [AMDGPU][MC] Support TFE modifiers in MUBUF loads and stores.
Reviewed By: dp, arsenm

Differential Revision: https://reviews.llvm.org/D137783
2022-11-14 15:36:18 +00:00
Dmitry Preobrazhensky
ef6f3c76f7 [AMDGPU][MC][GFX11] Improve diagnostic messages for invalid VOPD syntax
Differential Revision: https://reviews.llvm.org/D137842
2022-11-14 16:20:20 +03:00
Ivan Kosarev
926acd2bb5 [AMDGPU][AsmParser] Remove extra checks on missing instruction modifiers.
https://reviews.llvm.org/D137549 makes them unnecessary.

Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D137638
2022-11-10 12:49:27 +00:00
Pierre van Houtryve
7425077e31 [AMDGPU] Add & use hasNamedOperand, NFC
In a lot of places, we were just calling `getNamedOperandIdx` to check if the result was != or == to -1.
This is fine in itself, but it's verbose and doesn't make the intention clear, IMHO. I added a `hasNamedOperand` and replaced all cases I could find with regexes and manually.

Reviewed By: arsenm, foad

Differential Revision: https://reviews.llvm.org/D137540
2022-11-08 07:57:21 +00:00
Joe Nash
01b8140d3a [AMDGPU] Fix delay alu for VOPD with src2acc
V_FMAC_F32 and V_DOT2C_F32_F16 have a dummy src2 operand tied to vdst to
inform passes that the instructions read the dst operand. The VOPD
versions of these instructions lacked the dummy operand, which was a
problem for inserting s_delay_alu.
Introduce the dummy src2 operand on the VOPD versions, and fix the VOPD operand
tracking logic to account for it.

Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D136629
2022-10-25 13:11:17 -04:00