472 Commits

Author SHA1 Message Date
Nelson Chu
0b9a620b83 [RISCV] Support assembler and dis-assembler for VCIX extension.
Spec: https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf

Differential Revision: https://reviews.llvm.org/D144530
2023-04-09 20:41:01 -07:00
Michael Buch
8b0033e58a [ReleaseNotes] DebugInfo: preferred_name attribute changes
Describes changes made in D145803.

Differential Revision: https://reviews.llvm.org/D147695
2023-04-07 01:37:37 +01:00
Aaron Ballman
ceacb32524 Fix LLVM sphinx build
This addresses issues found by:
https://lab.llvm.org/buildbot/#/builders/30/builds/33698
2023-04-05 13:25:07 -04:00
Roy Sundahl
5f17ba1a38 [sanitizers] Simplify Explainer about dyld and weak overrides on Darwin. (NFC)
Presenting more than one way to satisfy the single-weak-ref requirement leads to
confusing messaging for the end user. Use the introduction of a single unused
weak variable as the preferred solution. This differential modifies D146745.

rdar://103453678

Reviewed By: yln, thetruestblue

Differential Revision: https://reviews.llvm.org/D147526
2023-04-05 10:04:29 -07:00
Archibald Elliott
0104305bc8 [NFC][AArch64] Late 2022 A-Profile Extension Release Notes 2023-04-04 11:39:41 +01:00
Roy Sundahl
f1c5c84ae1 [sanitizers] Explainer about dyld and weak overrides on Darwin. (NFC)
Explain in the release notes that the Darwin dynamic linker (dyld) requires
that at least one weak symbol be present in any mach-o file that defines an
intended override of a sanitizer dylib weak reference.

rdar://103453678

Reviewed By: thetruestblue

Differential Revision: https://reviews.llvm.org/D146745
2023-03-31 08:55:49 -07:00
Qiongsi Wu
f624372ccb [AIX][CodeGen] Renaming mroptr to xcoff-mroptr
This patch renames the `mroptr` option to `mxcoff-roptr` to indicate in the option itself that it is xcoff specific.

Reviewed By: hubert.reinterpretcast

Differential Revision: https://reviews.llvm.org/D147161
2023-03-31 10:09:48 -04:00
Craig Topper
dc90af501f [RISCV] Bump I, F, D, and A extension versions to 20191214 spec version
New versions I2.1, F2.2, D2.2 A2.1

Make F and Zfinx imply Zicsr.
Make G imply Zifencei.

This should have no impact to generated code. We have no plans to require Zicsr/Zifencei extension to be explicitly enabled to use Zicsr/Zifencei instructions in assembly.

See https://reviews.llvm.org/D147183 for documentation regarding what version specification we implement.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D147179
2023-03-30 15:28:44 -07:00
Alex Bradbury
d3291c692c [RISCV][MC] Add support for the experimental zicond extension
This patch adds the basic MC layer support for Zicond, based on
[1.0-rc1](https://github.com/riscv/riscv-zicond/releases/tag/v1.0-rc1).
As with other extensions, if there are additional changes between
release candidates without incrementing the version number we won't be
able to reflect that in the version number. I believe we've previously
decided this is not a problem for extensions still considered
experimental (i.e. not yet ratified).

Differential Revision: https://reviews.llvm.org/D146946
2023-03-29 12:17:50 +01:00
Wael Yehia
256914bf1c [AIX] Update release notes regarding -mxcoff-build-id and the profile runtime 2023-03-28 14:53:12 +00:00
Qiongsi Wu
4f9929add5 [AIX][CodeGen] Storage Locations for Constant Pointers
This patch adds an `llc` option `-mroptr` to specify storage locations for constant pointers on AIX.

When the `-mroptr` option is specified, constant pointers, virtual function tables, and virtual type tables are placed in read-only storage. Otherwise, by default, pointers, virtual function tables, and virtual type tables are placed are placed in read/write storage.

https://reviews.llvm.org/D144190 enables the `-mroptr` option for `clang`.

Reviewed By: hubert.reinterpretcast, stephenpeckham, myhsu, MaskRay, serge-sans-paille

Differential Revision: https://reviews.llvm.org/D144189
2023-03-23 09:44:47 -04:00
Job Noorman
c39dd7c1db [RISCV][MC] Add support for RV64E
Implement MC support for the recently ratified RV64E base instruction
set.

Differential Revision: https://reviews.llvm.org/D143570
2023-03-23 12:32:25 +00:00
David Spickett
85bc498826 [LLDB] Show sub type of signals when debugging a core file
Previously we only looked at the si_signo field, so you got:
```
(lldb) bt
* thread #1, name = 'a.out.mte', stop reason = signal SIGSEGV
  * frame #0: 0x00000000004007f4
```
This patch adds si_code so we can show:
```
(lldb) bt
* thread #1, name = 'a.out.mte', stop reason = signal SIGSEGV: sync tag check fault
  * frame #0: 0x00000000004007f4
```

The order of errno and code was incorrect in ElfLinuxSigInfo::Parse.
It was the order that a "swapped" siginfo arch would use, which for Linux,
is only MIPS. We removed MIPS Linux support some time ago.

See:
fe15c26ee2/include/uapi/asm-generic/siginfo.h (L121)

A test is added using memory tagging faults. Which were the original
motivation for the changes.

Reviewed By: JDevlieghere

Differential Revision: https://reviews.llvm.org/D146045
2023-03-21 09:10:09 +00:00
Austin Kerbow
09f756c880 [AMDGPU] Add release note for ommited barrier waitcnt
Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D146353
2023-03-19 21:15:28 -07:00
Mark de Wever
d0398d3593 Revert "Reland "[CMake] Bumps minimum version to 3.20.0.""
This reverts commit a72165e5df59032cdd54dcb18155f2630d73abd1.

Some buildbots have not been updated yet.
2023-03-18 20:32:43 +01:00
Mark de Wever
a72165e5df Reland "[CMake] Bumps minimum version to 3.20.0."
This reverts commit 92523a35a827539db8557bbc3ecab7f9ea3f6ade.

Test whether all CI runners are updated.
2023-03-18 13:33:42 +01:00
Paul Kirth
93c1a5f3dd [llvm-readobj] Rename JSON Flag fields to be more consistent
Today the JSON uses `Value` and `RawValue` when printing `Flags`, when really
the `Value` field is always the name of an Enum variant, and `RawValue` is its
underlying numeric value. Similarly, we rename the `RawFlags` key to `Value`,
to match the new scheme. This also allows JSON parsing to use consistent logic
for `Flag` types.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D137091
2023-03-18 00:04:47 +00:00
Aaron Ballman
d73c51bfda Fix LLVM Sphinx build
This addresses the issue found by:
https://lab.llvm.org/buildbot/#/builders/30/builds/33006
2023-03-16 14:03:39 -04:00
Arthur Eubanks
a63270cda8 [docs] Mention removal of legacy optimization pipeline and inliner alloca merging
Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D146243
2023-03-16 10:48:06 -07:00
Nikita Popov
bbfb13a5ff [ConstExpr] Remove select constant expression
This removes the select constant expression, as part of
https://discourse.llvm.org/t/rfc-remove-most-constant-expressions/63179.
Uses of this expressions have already been removed in advance,
so this just removes related infrastructure and updates tests.

Differential Revision: https://reviews.llvm.org/D145382
2023-03-16 10:32:08 +01:00
Arthur Eubanks
9e0c2626f3 [llvm-c] Remove pointee support from LLVMGetElementType
Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D145717
2023-03-09 15:42:38 -08:00
Nikita Popov
0aac9a2875 [llvm-c] Remove PassManagerBuilder APIs
The legacy PM is only supported for codegen, and PassManagerBuilder
is exclusively about the middle-end optimization pipeline. Drop it.

Differential Revision: https://reviews.llvm.org/D145387
2023-03-09 09:59:32 +01:00
Michael Buch
6a0f0fb190 [ReleaseNotes] Fix formatting for LLDB changes 2023-03-08 15:34:31 +00:00
Mark de Wever
92523a35a8 Revert "[CMake] Bumps minimum version to 3.20.0."
Some build bots have not been updated to the new minimal CMake version.
Reverting for now and ping the buildbot owners.

This reverts commit 44c6b905f8527635e49bb3ea97dea315f92d38ec.
2023-03-04 18:28:13 +01:00
Mark de Wever
44c6b905f8 [CMake] Bumps minimum version to 3.20.0.
This partly undoes D137724.

This change has been discussed on discourse
https://discourse.llvm.org/t/rfc-upgrading-llvms-minimum-required-cmake-version/66193

Note this does not remove work-arounds for older CMake versions, that
will be done in followup patches.

Reviewed By: mehdi_amini, MaskRay, ChuanqiXu, to268, thieta, tschuett, phosek, #libunwind, #libc_vendors, #libc, #libc_abi, sivachandra, philnik, zibi

Differential Revision: https://reviews.llvm.org/D144509
2023-03-04 12:40:57 +01:00
Vadim Paretsky
56e8fd6f6a [llvm-lib] update ReleaseNotes for llvm-lib's new support for generating
an import library from a definition file

Differential Revision:https://reviews.llvm.org/D145140
2023-03-03 10:54:27 -08:00
J. Ryan Stinnett
1572742cfa [DebugInfo][Docs] Remove dbg.addr from docs
Part of `dbg.addr` removal
Discussed in https://discourse.llvm.org/t/what-is-the-status-of-dbg-addr/62898

Differential Revision: https://reviews.llvm.org/D144792
2023-03-02 09:29:42 +00:00
Nikita Popov
f7ca013332 [llvm-c] Remove bindings for creating legacy passes
Legacy passes are only supported for codegen, and I don't believe
it's possible to write backends using the C API, so we should drop
all of those. Reduces the number of places that need to be modified
when removing legacy passes.

Differential Revision: https://reviews.llvm.org/D144970
2023-03-02 09:53:50 +01:00
Philipp Tomsich
f68f04d07c [RISCV] Add vendor-defined XTheadCondMov (conditional move) extension
The vendor-defined XTheadCondMov (somewhat related to the upcoming
Zicond and XVentanaCondOps) extension add conditional move
instructions with $rd being an input and an ouput instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=73442230966a22b3238b2074691a71d7b4ed914a

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144681
2023-02-24 21:40:42 +01:00
Matt Arsenault
5da674492a IR: Add nofpclass parameter attribute
This carries a bitmask indicating forbidden floating-point value kinds
in the argument or return value. This will enable interprocedural
-ffinite-math-only optimizations. This is primarily to cover the
no-nans and no-infinities cases, but also covers the other floating
point classes for free. Textually, this provides a number of names
corresponding to bits in FPClassTest, e.g.

  call nofpclass(nan inf) @must_be_finite()
  call nofpclass(snan) @cannot_be_snan()

This is more expressive than the existing nnan and ninf fast math
flags. As an added bonus, you can represent fun things like nanf:

  declare nofpclass(inf zero sub norm) float @only_nans()

Compared to nnan/ninf:
  - Can be applied to individual call operands as well as the return value
  - Can distinguish signaling and quiet nans
  - Distinguishes the sign of infinities
  - Can be safely propagated since it doesn't imply anything about
    other operands.
  - Does not apply to FP instructions; it's not a flag

This is one step closer to being able to retire "no-nans-fp-math" and
"no-infs-fp-math". The one remaining situation where we have no way to
represent no-nans/infs is for loads (if we wanted to solve this we
could introduce !nofpclass metadata, following along with
noundef/!noundef).

This is to help simplify the GPU builtin math library
distribution. Currently the library code has explicit finite math only
checks, read from global constants the compiler driver needs to set
based on the compiler flags during linking. We end up having to
internalize the library into each translation unit in case different
linked modules have different math flags. By propagating known-not-nan
and known-not-infinity information, we can automatically prune the
edge case handling in most functions if the function is only reached
from fast math uses.
2023-02-24 07:41:29 -04:00
Manolis Tsamis
7b79e8d455 [RISCV] Add vendor-defined XTheadFMemIdx (FP Indexed Memory Operations) extension
The vendor-defined XTHeadFMemIdx (no comparable standard extension exists
at the time of writing) extension adds indexed load/store instructions
for floating-point registers.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=f511f80fa3fcaf6bcbe727fb902b8bd5ec8f9c20

Depends on D144249

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144647
2023-02-24 00:35:37 +01:00
Manolis Tsamis
f6262201d8 [RISCV] Add vendor-defined XTheadMemIdx (Indexed Memory Operations) extension
The vendor-defined XTHeadMemIdx (no comparable standard extension exists
at the time of writing) extension adds indexed load/store instructions
as well as load/store and update register instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=27cfd142d0a7e378d19aa9a1278e2137f849b71b

Depends on D144002

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144249
2023-02-24 00:17:58 +01:00
Manolis Tsamis
16a6cf6a99 [RISCV] Add vendor-defined XTheadSync (Multi-core synchronization) extension
The vendor-defined XTheadSync (no comparable standard extension exists
at the time of writing) extension adds multi-core synchronization
instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=547c18d9bb95571261dbd17f4767194037eb82bd

Depends on D144496

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144501
2023-02-22 11:15:40 +01:00
Manolis Tsamis
f5b484c56f [RISCV] Add vendor-defined XTheadCmo (Cache Management Operations) extension
The vendor-defined XTHeadCmo (there are some similarities with the
Zicbom standard extension) extension adds cache management instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=a9ba8bc2d396fb8ae2b892f3bc6be8cdfe4b555c

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144496
2023-02-22 10:57:48 +01:00
Manolis Tsamis
bbb58a2302 [RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension
The vendor-defined XTHeadMemPair (no comparable standard extension exists
at the time of writing) extension adds two-GPR load/store pair instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=6e17ae625570ff8f3c12c8765b8d45d4db8694bd

Depends on D143847

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144002
2023-02-21 12:21:49 +01:00
Alex Bradbury
d41a73aa94 [RISCV][MC] Mark Zawrs extension as non-experimental
Support for the unratified 1.0-rc3 specification was introduced in
D133443. The specification has since been ratified (in November 2022
according to the recently ratified extensions list
<https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions>.

A review of the diff
<https://github.com/riscv/riscv-zawrs/compare/V1.0-rc3...main> of the
1.0-rc3 spec vs the current/ratified document shows no changes to the
instruction encoding or naming. At one point, a note was added
<e84f42406a>
indicating Zawrs depends on the Zalrsc extension (not officially
specified, but I believe to be just the LR/SC instructions from the A
extension). The final text ended up as "The instructions in the Zawrs
extension are only useful in conjunction with the LR instructions, which
are provided by the A extension, and which we also expect to be provided
by a narrower Zalrsc extension in the future." I think it's consistent
with this phrasing to not require the A extension for Zawrs, which
matches what was implemented.

No intrinsics are implemented for Zawrs currently, meaning we don't need
to additionally review whether those intrinsics can be considered
finalised and ready for exposure to end users.

Differential Revision: https://reviews.llvm.org/D143507
2023-02-19 20:43:03 +00:00
Philipp Tomsich
16a66af0a0 Revert "[RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension"
This reverts commit d2918544a7fc4b5443879fe12f32a712e6dfe325.
2023-02-17 19:45:55 +01:00
Manolis Tsamis
d2918544a7 [RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension
The vendor-defined XTHeadMemPair (no comparable standard extension exists
at the time of writing) extension adds two-GPR load/store pair instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=6e17ae625570ff8f3c12c8765b8d45d4db8694bd

Depends on D143847

Differential Revision: https://reviews.llvm.org/D144002
2023-02-17 19:45:22 +01:00
Manolis Tsamis
d4012bc43f [RISCV] Add vendor-defined XTheadMAC (multiply-accumulate) extension
The vendor-defined XTHeadMAC (no comparable standard extension exists
at the time of writing) extension adds multiply accumulate instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=4041e11db3ec3611921d10150572a92689aa3154

Co-authored-by: Philipp Tomsich <philipp.tomsich@vrull.eu>

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D143847
2023-02-14 20:25:47 +01:00
Krzysztof Parzyszek
e96f994f39 Revert "[Hexagon] Add release note for LLVM 16"
This reverts commit 140bc411b245260680d90fd981635317b261ef0e.

The release notes update has been backported to releases/16.x, and
can now be reverted in main.
2023-02-13 11:22:11 -08:00
Philipp Tomsich
fc02eeb24f [RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension
The vendor-defined XTHeadBb (predating the standard Zbb extension)
extension adds some bit-manipulation extensions with somewhat similar
semantics as some of the Zbb instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for XTHeadBb is
available from:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da

Depends on D143036

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D143439
2023-02-13 17:02:09 +01:00
Philipp Tomsich
04a2baf58f [RISCV] Add vendor-defined XTHeadBs (single-bit) extension
The vendor-defined XTHeadBs (predating the standard Zbs extension)
extension adds a bit-test instruction (th.tst) with similar semantics
as bexti from Zbs.  It is supported by the C9xx cores (e.g., found in
the wild in the Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for XTHeadBs is
available from:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D143036
2023-02-13 16:28:26 +01:00
Tobias Hieta
fff762d674
Revert "[CMake] Remove custom ccache CMake logic"
This reverts commit 0fad18c44a14b909a1aa47165021273d4c10a665.

We need bots to be updated first.
2023-02-13 08:57:19 +01:00
Tobias Hieta
0fad18c44a
[CMake] Remove custom ccache CMake logic
CMake supports CMAKE_CXX_COMPILER_LAUNCHER since CMake 3.4
so this custom CMake logic we had in LLVM can now be removed.

The only downside with this is that we can't set ccache
options from LLVM CMake, but it's arguable that this doesn't
belong in LLVM but should be done in a script calling the
build.

This was discussed in the forums here:

https://discourse.llvm.org/t/tips-for-incremental-building/67289/4?u=tobiashieta

Reviewed By: phosek

Differential Revision: https://reviews.llvm.org/D143468
2023-02-13 08:42:38 +01:00
Philipp Tomsich
0bda199285 Revert "[RISCV] Add vendor-defined XTHeadBs (single-bit) extension"
This reverts commit 656188ddc4075eb50260607b3497589873f373d2.
2023-02-08 08:00:45 +01:00
Philipp Tomsich
656188ddc4 [RISCV] Add vendor-defined XTHeadBs (single-bit) extension
The vendor-defined XTHeadBs (predating the standard Zbs extension)
extension adds a bit-test instruction (th.tst) with similar semantics
as bexti from Zbs.  It is supported by the C9xx cores (e.g., found in
the wild in the Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for XTHeadBs is
available from:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da

Depends on D143394

Differential Revision: https://reviews.llvm.org/D143036
2023-02-08 07:57:27 +01:00
Philipp Tomsich
e25b30d90a [RISCV] Add vendor-defined XTHeadBa (address-generation) extension
The vendor-defined XTHeadBa (predating the standard Zba extension)
extension adds an address-generation instruction (th.addsl) with
similar semantics as sh[123]add from Zba.  It is supported by the C9xx
cores (e.g., found in the wild in the Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for XTHeadBa is
available from:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D143029
2023-02-08 07:54:52 +01:00
Krzysztof Parzyszek
140bc411b2 [Hexagon] Add release note for LLVM 16 2023-02-07 09:25:21 -08:00
Craig Topper
2919ec041f [RISCV] Remove side effects from vsetvli intrinsics.
Delete the opt intrinsics since they are now identical.

I left the side effects due to user expectations about how these
interact with things like inline assembly or function calls. Or
that they wouldn't be hoisted. I think we should look at other
ways to address thoughs.

If I could, I'd rename them these somehow to distance them from
the vsetvli instruction. In some sense they only query the VL for
a particular SEW and LMUL. They don't guarantee a vsetvli
instruction will be emitted.

Fixes https://github.com/llvm/llvm-project/issues/59359

Reviewed By: rogfer01, kito-cheng

Differential Revision: https://reviews.llvm.org/D143220
2023-02-03 13:03:56 -08:00
Simon Tatham
60ea6f35a2 [ARM] Allow selecting hard-float ABI in integer-only MVE.
Armv8.1-M can be configured to support the integer subset of the MVE
vector instructions, and no floating point. In that situation, the FP
and vector registers still exist, and so do the load, store and move
instructions that transfer data in and out of them. So there's no
reason the hard floating point ABI can't be supported, and you might
reasonably want to use it, for the sake of intrinsics-based code
passing explicit MVE vector types between functions.

But the selection of the hard float ABI in the backend was gated on
Subtarget->hasVFP2Base(), which is false in the case of integer MVE
and no FP.

As a result, you'd silently get the soft float ABI even if you
deliberately tried to select it, e.g. with clang options such as
--target=arm-none-eabi -mfloat-abi=hard -march=armv8.1m.main+nofp+mve

The hard float ABI should have been gated on the weaker condition
Subtarget->hasFPRegs(), because the only requirement for being able to
pass arguments in the FP registers is that the registers themselves
should exist.

I haven't added a new test, because changing the existing
CodeGen/Thumb2/float-ops.ll test seemed sufficient. But I've added a
comment explaining why the results are expected to be what they are.

Reviewed By: lenary

Differential Revision: https://reviews.llvm.org/D142703
2023-02-01 09:05:12 +00:00