32325 Commits

Author SHA1 Message Date
Eric Christopher
09696d3fea Remove the need to cache the subtarget in the AArch64 TargetRegisterInfo
classes. Replace it with a cache to the Triple and use that
where applicable at the moment.

llvm-svn: 232005
2015-03-12 02:04:46 +00:00
Jingyue Wu
e8290f21b5 [NVPTXAsmPrinter] do not print .align on function headers
Summary:
PTX does not allow .align directives on function headers.

Fixes PR21551.

Test Plan: test/Codegen/NVPTX/function-align.ll

Reviewers: eliben, jholewinski

Reviewed By: eliben, jholewinski

Subscribers: llvm-commits, eliben, jpienaar, jholewinski

Differential Revision: http://reviews.llvm.org/D8274

llvm-svn: 232004
2015-03-12 01:50:30 +00:00
Eric Christopher
ea178cf48f Remove the need to cache the subtarget in the PowerPC TargetRegisterInfo
classes. Replace it with a cache to the TargetMachine and use that
where applicable at the moment.

llvm-svn: 232002
2015-03-12 01:42:51 +00:00
Krzysztof Parzyszek
325297c101 Fix build break introduced in r231992
llvm-svn: 231996
2015-03-12 00:49:13 +00:00
Krzysztof Parzyszek
6d5a4b5dcd Eliminate constant-extender profitability checks from Hexagon isel
llvm-svn: 231992
2015-03-12 00:19:59 +00:00
Mehdi Amini
93e1ea167e Move the DataLayout to the generic TargetMachine, making it mandatory.
Summary:
I don't know why every singled backend had to redeclare its own DataLayout.
There was a virtual getDataLayout() on the common base TargetMachine, the
default implementation returned nullptr. It was not clear from this that
we could assume at call site that a DataLayout will be available with
each Target.

Now getDataLayout() is no longer virtual and return a pointer to the
DataLayout member of the common base TargetMachine. I plan to turn it into
a reference in a future patch.

The only backend that didn't have a DataLayout previsouly was the CPPBackend.
It now initializes the default DataLayout. This commit is NFC for all the
other backends.

Test Plan: clang+llvm ninja check-all

Reviewers: echristo

Subscribers: jfb, jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D8243

From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 231987
2015-03-12 00:07:24 +00:00
Hal Finkel
6a778fb7c2 [PowerPC] Remove canFoldAsLoad from instruction definitions
The PowerPC backend had a number of loads that were marked as canFoldAsLoad
(and I'm partially at fault here for copying around the relevant line of
TableGen definitions without really looking at what it meant). This is not
right; PPC (non-memory) instructions don't support direct memory operands, and
so there is nothing a 'foldable' instruction could be folded into.

Noticed by inspection, no test case.

The one thing we might lose by doing this is ability to fold some loads into
stackmap/patchpoint pseudo-instructions. However, this was untested, and would
not obviously have worked for extending loads, and I'd rather re-add support
for that once it can be tested.

llvm-svn: 231982
2015-03-11 23:28:38 +00:00
Eric Christopher
5f141b03fa Remove useMachineScheduler and replace it with subtarget options
that control, individually, all of the disparate things it was
controlling.

At the same time move a FIXME in the Hexagon port to a new
subtarget function that will enable a user of the machine
scheduler to avoid using the source scheduler for pre-RA-scheduling.
The FIXME would have this removed, but involves either testcase
changes or adding -pre-RA-sched=source to a few testcases.

llvm-svn: 231980
2015-03-11 22:56:10 +00:00
Eric Christopher
9deb75d176 Have getCallPreservedMask and getThisCallPreservedMask take a
MachineFunction argument so that we can grab subtarget specific
features off of it.

llvm-svn: 231979
2015-03-11 22:42:13 +00:00
Eric Christopher
ec8cda5668 One more getCalleeSavedRegs prototype with nullptr.
llvm-svn: 231977
2015-03-11 22:24:37 +00:00
Eric Christopher
7af9528747 Have getCalleeSavedRegs take a non-null MachineFunction all the
time. The target independent code was passing in one all the
time and targets weren't checking validity before using. Update
a few calls to pass in a MachineFunction where necessary.

llvm-svn: 231970
2015-03-11 21:41:28 +00:00
Pete Cooper
d987cd2f31 Constify AArch64CollectLOH.cpp. NFC
llvm-svn: 231969
2015-03-11 21:40:25 +00:00
Jozef Kolek
4468947fce [mips][microMIPS] Make usage of NOT16 by code generator
Differential Revision: http://reviews.llvm.org/D7748

llvm-svn: 231963
2015-03-11 20:28:31 +00:00
Tim Northover
8cda34f5e7 ARM: simplify and extend byval handling
The main issue being fixed here is that APCS targets handling a "byval align N"
parameter with N > 4 were miscounting what objects were where on the stack,
leading to FrameLowering setting the frame pointer incorrectly and clobbering
the stack.

But byval handling had grown over many years, and had multiple layers of cruft
trying to compensate for each other and calculate padding correctly. This only
really needs to be done once, in the HandleByVal function. Elsewhere should
just do what it's told by that call.

I also stripped out unnecessary APCS/AAPCS distinctions (now that Clang emits
byvals with the correct C ABI alignment), which simplified HandleByVal.

rdar://20095672

llvm-svn: 231959
2015-03-11 18:54:22 +00:00
Eric Christopher
6c5b511b4d Remove the need to cache the subtarget in the R600 TargetRegisterInfo
classes.

llvm-svn: 231954
2015-03-11 18:43:21 +00:00
Eric Christopher
4320495319 Have getRegPressureSetLimit take a MachineFunction so that a
we can inspect the subtarget and function when computing values.

llvm-svn: 231951
2015-03-11 18:34:58 +00:00
Kit Barton
116e18be41 Updated with list of possible improvements we are tracking internally
llvm-svn: 231946
2015-03-11 17:43:43 +00:00
Juergen Ributzka
0c598cdaf1 Add the "vbroadcasti128" instruction back.
This is a follow-up to r231182. This adds the "vbroadcasti128" instruction
back, but without the intrinsic mapping. Also add a test to check the
instriction encoding.

This is related to rdar://problem/18742778.

llvm-svn: 231945
2015-03-11 17:29:03 +00:00
Derek Schuff
072f93fe72 Make NaCl's use of .init_array for static constructors match Linux
Summary:
The generic ELF TargetObjectFile defaults to .ctors, but Linux's
defaults to .init_array by calling InitializeELF with the value of
UseInitArray from TargetMachine. Make NaCl's behavior match.

Reviewers: jvoung
Differential Revision: http://reviews.llvm.org/D8240

llvm-svn: 231934
2015-03-11 16:16:09 +00:00
Elena Demikhovsky
0b9dbe33aa AVX-512: Added SKX forms of shift instructions.
Added rotation instructions, encoding only.
Added encoding tests for all these forms.

llvm-svn: 231916
2015-03-11 10:25:42 +00:00
Eric Christopher
433c432b7e Have TargetRegisterInfo::getLargestLegalSuperClass take a
MachineFunction argument so that it can look up the subtarget
rather than using a cached one in some Targets.

llvm-svn: 231888
2015-03-10 23:46:01 +00:00
Eric Christopher
c4d3140524 Remove subtarget dependence from HexagonRegisterInfo.
llvm-svn: 231887
2015-03-10 23:45:55 +00:00
Eric Christopher
49338e9fa6 Remove dead code.
llvm-svn: 231883
2015-03-10 23:22:04 +00:00
Eric Christopher
0169e42c3b Remove the use of the subtarget in MCCodeEmitter creation and
update all ports accordingly. Required a couple of small rewrites
in handling subtarget features during creation in PPC.

llvm-svn: 231861
2015-03-10 22:03:14 +00:00
Rafael Espindola
6b9998b3eb Create symbols marking the start of a section earlier.
This lets us pass the symbol to the constructor and avoid the mutable field.

This also opens the way for outputting the symbol only when needed, instead
of outputting them at the start of the file.

llvm-svn: 231859
2015-03-10 22:00:25 +00:00
Eric Christopher
501d5e9f66 Remove createAMDGPUMCCodeEmitter and instead just register the correct
MCCodeEmitter creation routine based on TargetMachine since the only
64-bit R600 gpus are part of the GCN target.

llvm-svn: 231856
2015-03-10 21:57:34 +00:00
Colin LeMahieu
bdc6c83d24 [Hexagon] Adding frame index + add load/store patterns.
llvm-svn: 231850
2015-03-10 21:24:13 +00:00
Colin LeMahieu
3901c066e0 [Hexagon] Simplifying deallocret definitions.
llvm-svn: 231847
2015-03-10 21:12:32 +00:00
Colin LeMahieu
4e90d2136f [Hexagon] Separating InstHexagon from OpcodeHexagon.
llvm-svn: 231844
2015-03-10 20:56:22 +00:00
Nemanja Ivanovic
0adf26b9b0 Add support for part-word atomics for PPC
http://reviews.llvm.org/D8090#inline-67337

llvm-svn: 231843
2015-03-10 20:51:07 +00:00
Ahmed Bougacha
fab5892f8b [AArch64] Avoid going through GPRs for across-vector instructions.
This adds new node types for each intrinsic.
For instance, for addv, we have AArch64ISD::UADDV, such that:
  (v4i32 (uaddv ...))
is the same as
  (v4i32 (scalar_to_vector (i32 (int_aarch64_neon_uaddv ...))))
that is,
  (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
           (i32 (int_aarch64_neon_uaddv ...)), ssub)

In a combine, we transform all such across-vector-lanes intrinsics to:

  (i32 (extract_vector_elt (uaddv ...), 0))

This has one big advantage: by making the extract_element explicit, we
enable the existing patterns for lane-aware instructions to fire.
This lets us avoid needlessly going through the GPRs.  Consider:

    uint32x4_t test_mul(uint32x4_t a, uint32x4_t b) {
        return vmulq_n_u32(a, vaddvq_u32(b));
    }

We now generate:
    addv.4s  s1, v1
    mul.4s   v0, v0, v1[0]
instead of the previous:
    addv.4s  s1, v1
    fmov     w8, s1
    dup.4s   v1, w8
    mul.4s   v0, v1, v0

rdar://20044838

llvm-svn: 231840
2015-03-10 20:45:38 +00:00
Ahmed Bougacha
8f6a115de9 [AArch64] Remove integer INSvi*lane patterns. NFCI.
Most are redundant, and they never seem to fire.

The V128 integer patterns already exist in the INS multiclass.
The duplicates only fire when the vector index type isn't i64,
because they accept "imm" instead of an explicit "i64", as the
instruction definition patterns do.

TLI::getVectorIdxTy is i64 on AArch64, so this should never happen.
Also, one of them had a typo: for i64, INSvi32lane was used.
I noticed because I mistakenly used an explicit i32 as the idx type,
and got ins.s for an i64 vector_insert.

The V64 patterns also don't seem to ever fire, as V64 vector
extract/insert are legalized to V128.

The equivalent float patterns are unique and useful, so keep them.

No functional change intended;  none exhibited on the LIT and LNT tests.

llvm-svn: 231838
2015-03-10 20:37:19 +00:00
Benjamin Kramer
d58792f38b Don't use LLVM_LIBRARY_VISIBILITY in cpp files.
llvm-svn: 231831
2015-03-10 20:07:44 +00:00
Colin LeMahieu
60a99e66a0 [Hexagon] Adding nodes for PIC support.
llvm-svn: 231829
2015-03-10 20:04:44 +00:00
Colin LeMahieu
092d9c18a8 [Hexagon] Adding DuplexInst instruction format and duplex class defs.
llvm-svn: 231828
2015-03-10 19:53:14 +00:00
Kit Barton
20d3981e15 Change the generation of the vmuluwm instruction to be based on the MUL opcode.
Phabricator review: http://reviews.llvm.org/D8185

llvm-svn: 231827
2015-03-10 19:49:38 +00:00
Colin LeMahieu
3b6747df13 [Hexagon] Adding nodes for vector insert/extract lowering.
llvm-svn: 231825
2015-03-10 19:40:03 +00:00
Colin LeMahieu
ee776452f9 [Hexagon] Renaming HexagonJT to JT and adding CP for constantpool.
llvm-svn: 231824
2015-03-10 19:29:53 +00:00
Benjamin Kramer
414c0964c3 NVPTX: move NVPTXAllocaHoisting into the cpp file
Also initialize without using static initialization.

llvm-svn: 231822
2015-03-10 19:20:52 +00:00
Benjamin Kramer
42a31e1f5e NVPTX: Remove copy of LLVMInitializeNVPTXAsmPrinter.
If anyone is using this for some strange reason,
LLVMInitializeNVPTXAsmPrinter does exactly the same thing and is what
other LLVM tools are calling.

llvm-svn: 231810
2015-03-10 18:19:24 +00:00
Benjamin Kramer
9d1f2dfec7 Hexagon: Remove unused InstrMapping.
llvm-svn: 231809
2015-03-10 18:19:16 +00:00
Tom Stellard
a14b0114a3 R600/SI: Add _IDXEN and _BOTHEN variants for buffer_store
llvm-svn: 231798
2015-03-10 16:16:51 +00:00
Tom Stellard
c229baa94c R600/SI: Re-order MUBUF operands to match asm strings.
llvm-svn: 231797
2015-03-10 16:16:49 +00:00
Tom Stellard
4d6c99ddf2 R600/SI: Move kill flag to second instruction when splitting SMRD
This fixes a machine verifier error in the salu-to-valu.ll, which
would have been exposed by a future commit.

llvm-svn: 231796
2015-03-10 16:16:48 +00:00
Tom Stellard
5224df36c8 R600/SI: Add 32-bit encoding of v_cndmask_b32
This was done by refactoring the v_cndmask_b32 tablegen definition
to use inherit from VOP2Inst.

llvm-svn: 231795
2015-03-10 16:16:44 +00:00
Benjamin Kramer
4683395808 Hexagon: Remove pass that does nothing at all
llvm-svn: 231791
2015-03-10 15:06:38 +00:00
Aaron Ballman
f00fd1f087 Removing dead code to silence warning C4060: switch statement contains no 'case' or 'default' labels; NFC.
llvm-svn: 231785
2015-03-10 13:56:28 +00:00
Rafael Espindola
760bf9520a Remove incredibly confusing isBaseAddressKnownZero.
When referring to a symbol in a dwarf section on ELF we should use

.long foo

instead of

.long foo - .debug_something

because ELF is unaware of the content of the sections and therefore needs
relocations. This has nothing to do with optimizing a -0.

llvm-svn: 231751
2015-03-10 04:11:52 +00:00
Rafael Espindola
fcc2821882 Use a better name for compile unit labels.
They mark the start of a compile unit, so name them .Lcu_*. Using
Section->getLabelBeginName() makes it looks like they mark the start of the
section.

While at it, switch to createTempSymbol to avoid collisions with labels
created in inline assembly. Not sure if a "don't crash" test is worth it.

With this getLabelBeginName is dead, delete it.

llvm-svn: 231750
2015-03-10 03:58:36 +00:00
Mehdi Amini
a28d91d81b DataLayout is mandatory, update the API to reflect it with references.
Summary:
Now that the DataLayout is a mandatory part of the module, let's start
cleaning the codebase. This patch is a first attempt at doing that.

This patch is not exactly NFC as for instance some places were passing
a nullptr instead of the DataLayout, possibly just because there was a
default value on the DataLayout argument to many functions in the API.
Even though it is not purely NFC, there is no change in the
validation.

I turned as many pointer to DataLayout to references, this helped
figuring out all the places where a nullptr could come up.

I had initially a local version of this patch broken into over 30
independant, commits but some later commit were cleaning the API and
touching part of the code modified in the previous commits, so it
seemed cleaner without the intermediate state.

Test Plan:

Reviewers: echristo

Subscribers: llvm-commits

From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 231740
2015-03-10 02:37:25 +00:00