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18 Commits

Author SHA1 Message Date
Krzysztof Parzyszek
b2c458e648 [Hexagon] SETEQ and SETNE are valid integer condition codes 
llvm-svn: 323452
 2018-01-25 18:07:27 +00:00
Krzysztof Parzyszek
cf3ad5841b [Hexagon] Run late copy propagation and dead code elimination passes 
llvm-svn: 323346
 2018-01-24 17:48:11 +00:00
Krzysztof Parzyszek
3780a0e1fa [Hexagon] Implement basic vector operations on vectors vNi1 
In addition to that, make sure that there are no boolean vector types that
are associated with multiple register classes. Specifically, remove v32i1
and v64i1 from integer register classes. These types will correspond to
results of vector comparisons, and as such should belong to the vector
predicate class. Having them in scalar registers as well makes legalization
ambiguous.

llvm-svn: 323229
 2018-01-23 17:53:59 +00:00
Krzysztof Parzyszek
b8f2a1e7b7 [Hexagon] Rewrite LowerVECTOR_SHUFFLE for 32-/64-bit vectors 
The old implementation was not always correct. The new one recognizes
more shuffles that match specific instructions.

llvm-svn: 322498
 2018-01-15 18:33:33 +00:00
Krzysztof Parzyszek
240df6faa4 [Hexagon] Fix building 64-bit vector from constant values 
The constants were aggregated in a reverse order.

llvm-svn: 322303
 2018-01-11 18:30:41 +00:00
Krzysztof Parzyszek
66ee123d61 [Hexagon] Add pattern for vsplat to v8i8 
llvm-svn: 321892
 2018-01-05 20:43:56 +00:00
Krzysztof Parzyszek
e4ce92cabf [Hexagon] Allow construction of HVX vector predicates 
Handle BUILD_VECTOR of boolean values.

llvm-svn: 321220
 2017-12-20 20:49:43 +00:00
Krzysztof Parzyszek
8f6b0c850a [Hexagon] Adjust the value type for BCvt in LowerFormalArguments 
llvm-svn: 321177
 2017-12-20 14:44:05 +00:00
Krzysztof Parzyszek
f4dcc42e7b [Hexagon] Remove HexagonISD::PACKHL 
llvm-svn: 319352
 2017-11-29 19:59:29 +00:00
Krzysztof Parzyszek
942fa1631f [Hexagon] Implement buildVector32 and buildVector64 as utility functions 
Change LowerBUILD_VECTOR to use those functions. This commit will tempora-
rily affect constant vector generation (it will generate constant-extended
values instead of non-extended combines), but the code for the general case
should be better. The constant selection part will be fixed later.

llvm-svn: 318877
 2017-11-22 20:56:23 +00:00
Krzysztof Parzyszek
64e5d7d3ae [Hexagon] Reorganize and update instruction patterns 
llvm-svn: 316228
 2017-10-20 19:33:12 +00:00
Ron Lieberman
f90493d220 [Hexagon] Patch to Extract i1 element from vector of i1 
This patch extracts 1 element from vector consisting
of elements of size 1 bit at given index.

llvm-svn: 314641
 2017-10-02 00:16:15 +00:00
Krzysztof Parzyszek
5eef92eb7f [Hexagon] Remove custom lowering of loads of v4i16 
The target-independent lowering works fine, except concatenating 32-bit
words. Add a pattern to generate A2_combinew instead of 64-bit asl/or.

llvm-svn: 308186
 2017-07-17 15:45:45 +00:00
Krzysztof Parzyszek
33fd0bbbe8 [Hexagon] Generate extract instructions more aggressively 
llvm-svn: 296537
 2017-02-28 23:27:33 +00:00
Krzysztof Parzyszek
a72fad980c [Hexagon] Replace instruction definitions with auto-generated ones 
llvm-svn: 294753
 2017-02-10 15:33:13 +00:00
Krzysztof Parzyszek
167d918225 [Hexagon] Implement MI-level constant propagation 
llvm-svn: 277028
 2016-07-28 20:01:59 +00:00
Krzysztof Parzyszek
a7c5f0409c [Hexagon] Split double registers 
llvm-svn: 250549
 2015-10-16 20:38:54 +00:00
Krzysztof Parzyszek
421133470f [Hexagon] Add support for vector instructions 
llvm-svn: 232728
 2015-03-19 16:33:08 +00:00