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23663 Commits

Author SHA1 Message Date
Dan Gohman
8a361c1f92 Basic feature test for multiple return values in codegen. 
llvm-svn: 48260
 2008-03-11 23:53:16 +00:00
Anton Korobeynikov
80b53b8f6b Testcase for PR2137 
llvm-svn: 48258
 2008-03-11 22:43:42 +00:00
Anton Korobeynikov
6f51973734 Update testcase for recent aliases change 
llvm-svn: 48250
 2008-03-11 21:42:20 +00:00
Dan Gohman
6616836e71 Add a test to ensure that all-ones vectors are materialized with pcmpeqd. 
llvm-svn: 48247
 2008-03-11 21:37:00 +00:00
Dan Gohman
44b4c07cd1 Use the correct value for InSignBit. 
llvm-svn: 48245
 2008-03-11 21:29:43 +00:00
Chris Lattner
8abed80a69 Implement basic support for the 'f' register class constraint. This basically 
works, but probably won't if you mix it with 't' or 'u' yet.

llvm-svn: 48243
 2008-03-11 19:50:13 +00:00
Dale Johannesen
1b12647544 The feature this is testing did not work in the general case, 
and has been removed.

llvm-svn: 48232
 2008-03-11 17:48:26 +00:00
Evan Cheng
34e5b34426 Learn how to xfail a test. 
llvm-svn: 48219
 2008-03-11 07:51:31 +00:00
Evan Cheng
e88a625ecd When the register allocator runs out of registers, spill a physical register around the def's and use's of the interval being allocated to make it possible for the interval to target a register and spill it right away and restore a register for uses. This likely generates terrible code but is before than aborting. 
llvm-svn: 48218
 2008-03-11 07:19:34 +00:00
Evan Cheng
756f9d9c51 XFAIL due to Dale's change. 
llvm-svn: 48216
 2008-03-11 07:15:44 +00:00
Dan Gohman
d6819da453 Generalize ExpandIntToFP to handle the case where the operand is legal 
and it's the result that requires expansion. This code is a little confusing
because the TargetLoweringInfo tables for [US]INT_TO_FP use the operand type
(the integer type) rather than the result type. 

llvm-svn: 48206
 2008-03-11 01:59:03 +00:00
Scott Michel
92275427e5 - Style cleanup in IA64ISelLowering.h: add 'virtual' keyword for consistency. 
- Add test pattern matching in CellSPU's icmp32.ll test harness
- Fix CellSPU fcmp.ll-generated assert.

llvm-svn: 48197
 2008-03-10 23:49:09 +00:00
Chris Lattner
7362d38391 Don't emit FP_REG_KILL into a block that just returns. Nothing 
can be live out of the block anyway, so it isn't needed.

llvm-svn: 48192
 2008-03-10 23:34:12 +00:00
Dan Gohman
f4300950f1 Implement more support for fp-to-i128 and i128-to-fp conversions. 
llvm-svn: 48189
 2008-03-10 23:03:31 +00:00
Bill Wendling
24155f7381 Update llc flags for PPC register scavenger. 
llvm-svn: 48187
 2008-03-10 22:59:08 +00:00
Dan Gohman
272e234477 Fix mul expansion to check the correct number of bits for 
zero extension when checking if an unsigned multiply is
safe.

llvm-svn: 48171
 2008-03-10 20:42:19 +00:00
Dale Johannesen
fe2c0e2dca These tests don't work unless SSE2 is active. 
Judging from the checking comments this is intentional,
so add the flag (makes them pass on non-x86 host).

llvm-svn: 48157
 2008-03-10 17:33:57 +00:00
Dale Johannesen
65aada6e8f There is no "-mattr=+sse1" flag; fix test for non-x86 hosts. 
llvm-svn: 48156
 2008-03-10 17:13:37 +00:00
Scott Michel
48e3375544 Integer comparison tests for CellSPU. 
llvm-svn: 48152
 2008-03-10 16:58:52 +00:00
Evan Cheng
4a3c5eab34 - Fix a subtle bug in RemoveCopyByCommutingDef. ALR is the live range where the source is defined; BLR is the live range which is defined by the copy. 
If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.                                                                                                 
 A = or A, B                                                                                                                                                            
 ...                                                                                                                                                                    
 B = A                                                                                                                                                                  
 ...                                                                                                                                                                    
 C = A<kill>                                                                                                                                                            
 ...                                                                                                                                                                    
   = B                                                                                                                                                                  
                                                                                                                                                                        
then do not add kills of A to the newly created B interval.
- Also fix some kill info update bug.

llvm-svn: 48141
 2008-03-10 08:11:32 +00:00
Evan Cheng
b5d11980d9 Avoid creating BUILD_VECTOR of all zero elements of "non-normalized" type (e.g. v8i16 on x86) after legalizer. Instruction selection does not expect to see them. In all likelihood this can only be an issue in a bugpoint reduced test case. 
llvm-svn: 48136
 2008-03-10 07:19:13 +00:00
Chris Lattner
176542a970 remove an execution test. 
llvm-svn: 48135
 2008-03-10 06:53:14 +00:00
Evan Cheng
b46ec99b7e Fix RUN line. 
llvm-svn: 48116
 2008-03-09 19:55:22 +00:00
Chris Lattner
86829f0ff7 teach X86InstrInfo::copyRegToReg how to copy into ST(0) from 
an RFP register class.

Teach ScheduleDAG how to handle CopyToReg with different src/dst 
reg classes.

This allows us to compile trivial inline asms that expect stuff
on the top of x87-fp stack.

llvm-svn: 48107
 2008-03-09 09:15:31 +00:00
Chris Lattner
9e07537e8c Add ScheduleDAG support for copytoreg where the src/dst register are 
in different register classes, e.g. copy of ST(0) to RFP*.  This gets
some really trivial inline asm working that plops things on the top of
stack (PR879)

llvm-svn: 48105
 2008-03-09 08:49:15 +00:00
Tanya Lattner
aa6f5c9ddd Remove llvm-upgrade and update tests. 
llvm-svn: 48103
 2008-03-09 08:16:40 +00:00
Chris Lattner
a6ce71fb84 reduce this testcase more 
llvm-svn: 48092
 2008-03-09 06:57:21 +00:00
Chris Lattner
b6387c8a74 Finish implementing a readme entry: when inserting an i64 variable 
into a vector of zeros or undef, and when the top part is obviously
zero, we can just use movd + shuffle.  This allows us to compile
vec_set-B.ll into:

_test3:
	movl	$1234567, %eax
	andl	4(%esp), %eax
	movd	%eax, %xmm0
	ret

instead of:

_test3:
	subl	$28, %esp
	movl	$1234567, %eax
	andl	32(%esp), %eax
	movl	%eax, (%esp)
	movl	$0, 4(%esp)
	movq	(%esp), %xmm0
	addl	$28, %esp
	ret

llvm-svn: 48090
 2008-03-09 05:42:06 +00:00
Chris Lattner
eef374c197 Implement a readme entry, compiling 
#include <xmmintrin.h>
__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}

into:
	movl	$1, %eax
	movd	%eax, %xmm0
	ret

instead of a constant pool load.

llvm-svn: 48063
 2008-03-09 01:05:04 +00:00
Chris Lattner
3ed815a3a5 upgrade this test 
llvm-svn: 48062
 2008-03-09 00:32:10 +00:00
Chris Lattner
031e04b7a3 make this test harder 
llvm-svn: 48061
 2008-03-09 00:30:06 +00:00
Chris Lattner
a1f25b0020 Teach SD some vector identities, allowing us to compile vec_set-9 into: 
_test3:
	movd	%rdi, %xmm1
	#IMPLICIT_DEF %xmm0
	punpcklqdq	%xmm1, %xmm0
	ret

instead of:

_test3:
	#IMPLICIT_DEF %rax
	movd	%rax, %xmm0
	movd	%rdi, %xmm1
	punpcklqdq	%xmm1, %xmm0
	ret

This is still not ideal.  There is no reason to two xmm regs.

llvm-svn: 48058
 2008-03-08 23:43:36 +00:00
Evan Cheng
95cf661534 Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions. 
llvm-svn: 48042
 2008-03-08 00:58:38 +00:00
Dan Gohman
d2ab5fd713 Add support for calls with i128 return values on ppc64. 
llvm-svn: 48041
 2008-03-08 00:19:12 +00:00
Dan Gohman
8d2ead2e34 Add support for lowering 128-bit shifts on ppc64. 
llvm-svn: 48029
 2008-03-07 20:36:53 +00:00
Evan Cheng
39a3221e27 Fixed a register scavenger bug. If a def is re-defining part of a super register, there must be an implicit def of the super-register on the MI. 
llvm-svn: 48024
 2008-03-07 20:12:54 +00:00
Chris Lattner
d4defb00df mark frem as expand for all legal fp types on x86, regardless of whether 
we're using SSE or not.  This fixes PR2122.

llvm-svn: 48006
 2008-03-07 06:36:32 +00:00
Bill Wendling
92e52c636f Add testcase. 
llvm-svn: 48005
 2008-03-06 23:34:22 +00:00
Gabor Greif
636ab19205 some more spelling changes 
llvm-svn: 47996
 2008-03-06 10:51:21 +00:00
Evan Cheng
a3cb090446 Constant fold SIGN_EXTEND_INREG with ashr not lshr. 
llvm-svn: 47992
 2008-03-06 08:20:51 +00:00
Scott Michel
e9b690b7f1 Refine Cell's i64 constant generation code to cover more constants where the 
upper and lower 32-bits are the same (in addition to 0 and -1 previously.)

llvm-svn: 47985
 2008-03-06 04:02:54 +00:00
Scott Michel
48072bf179 - Expand tabs to spaces. 
- select_bits.ll now fully functional now that PR1993 is closed. It was
  previously broken by refactoring in SPUInstrInfo.td and using multiclasses.
- Same for eqv.ll

llvm-svn: 47972
 2008-03-05 23:00:19 +00:00
Evan Cheng
29b502e0e0 Fix a coalescer bug wrt how dead copy interval is shortened. 
llvm-svn: 47966
 2008-03-05 22:09:42 +00:00
Chris Lattner
78e9cab229 Generalize FP constant shrinking optimization to apply to any vt 
except ppc long double.  This allows us to shrink constant pool
entries for x86 long double constants, which in turn allows us to
use flds/fldl instead of fldt.

llvm-svn: 47938
 2008-03-05 06:48:13 +00:00
Evan Cheng
0a62cb44ce Add a target lowering hook to control whether it's worthwhile to compress fp constant. 
For x86, if sse2 is available, it's not a good idea since cvtss2sd is slower than a movsd load and it prevents load folding. On x87, it's important to shrink fp constant since fldt is very expensive.

llvm-svn: 47931
 2008-03-05 01:30:59 +00:00
Bill Wendling
09de8e494e Use -enable-ppc-regscavenger flag for these checks 
llvm-svn: 47916
 2008-03-04 23:16:26 +00:00
Evan Cheng
16e2cf6db1 Really fix the test. 
llvm-svn: 47882
 2008-03-04 08:01:56 +00:00
Evan Cheng
7473c74d52 Fix broken test. 
llvm-svn: 47881
 2008-03-04 07:59:13 +00:00
Evan Cheng
62240d65fd Add PR1501 test case. 
llvm-svn: 47874
 2008-03-04 00:47:45 +00:00
Bill Wendling
632ea65072 This is the initial check-in for adding register scavenging to PPC. (Currently, 
PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that
it uses a register other than the default R0 register (the scavenger scrounges
for one). A significant part of this patch fixes how kill information is
handled.

llvm-svn: 47863
 2008-03-03 22:19:16 +00:00