284057 Commits

Author SHA1 Message Date
Simon Pilgrim
94ea374b18 [X86][SSE] Regenerate odd sized sext/zext tests
llvm-svn: 326484
2018-03-01 21:13:26 +00:00
Matt Arsenault
1422a19a88 AMDGPU/GlobalISel: Use a more correct getValueMapping
This was finding the wrong size registers for anything with
more than 2 components.

Patch by Tom Stellard

llvm-svn: 326483
2018-03-01 21:08:51 +00:00
Matt Arsenault
62669ede94 AMDGPU/GlobalISel: Define instruction mapping for G_BITCAST
Patch by Tom Stellard

llvm-svn: 326482
2018-03-01 20:59:44 +00:00
Matt Arsenault
0529a8e2de AMDGPU/GlobalISel: Mark i32->i64 zext as legal
llvm-svn: 326481
2018-03-01 20:56:21 +00:00
Martin Storsjo
c61ff3bef1 [AArch64] Add support for secrel add/load/store relocations for COFF
Differential Revision: https://reviews.llvm.org/D43288

llvm-svn: 326480
2018-03-01 20:42:28 +00:00
Matt Arsenault
36b99e1937 AMDGPU/GlobalISel: InstrMapping for llvm.amdgcn.exp.compr
Patch by Tom Stellard

llvm-svn: 326479
2018-03-01 20:40:55 +00:00
Rui Ueyama
b34bd34fd2 [MinGW] Fix --{start,end}-group.
Currently --start-group=foo is accidentally accepted by the MinGW driver.

Differential Revision: https://reviews.llvm.org/D43836

llvm-svn: 326478
2018-03-01 20:38:38 +00:00
Matt Arsenault
8931bbf8df AMDGPU/GlobalISel: Define instruction mapping for @llvm.amdgcn.exp
Patch by Tom Stellard

llvm-svn: 326477
2018-03-01 20:24:37 +00:00
Martin Storsjo
87c2ad29ee [RecordLayout] Only assert that fundamental type sizes are power of two on MSVC
Make types with sizes that aren't a power of two an error (that can
be disabled) in structs with ms_struct layout, except on mingw where
the situation is quite likely to occur and GCC handles it silently.

Differential Revision: https://reviews.llvm.org/D43908

llvm-svn: 326476
2018-03-01 20:22:57 +00:00
Craig Topper
2915bc0046 [SimplifyLibCalls] Update an obviously copy and pasted header comment to match this file. NFC
llvm-svn: 326475
2018-03-01 20:05:09 +00:00
Craig Topper
f1a7c6755d [InstCombine] Auto-generate complete checks. NFC
llvm-svn: 326474
2018-03-01 20:05:07 +00:00
Matt Arsenault
50721ab325 AMDGPU/GlobalISel: Define InstrMappings for G_ICMP
Patch by Tom Stellard

llvm-svn: 326472
2018-03-01 19:27:10 +00:00
Matt Arsenault
dc14ec05d4 AMDGPU/GlobalISel: Make i32 mul legal
llvm-svn: 326471
2018-03-01 19:22:05 +00:00
Matt Arsenault
06cbb27a79 AMDGPU/GlobalISel: Define instruction mapping for G_IMPLICIT_DEF
Patch by Tom Stellard

llvm-svn: 326470
2018-03-01 19:16:52 +00:00
Saleem Abdulrasool
cc6238158a Driver: hoist -fno-rtti-data to a driver flag
This is needed for building with the GNU driver (`clang++`) when
targeting Windows and using msvcprt.  This flag is the equivalent of
`/GR-`.

llvm-svn: 326469
2018-03-01 19:13:43 +00:00
Matt Arsenault
e3d9ecf2b9 AMDGPU/GlobalISel: Define instruction mapping for G_FCONSTANT
Patch by Tom Stellard

llvm-svn: 326468
2018-03-01 19:13:30 +00:00
Matt Arsenault
51b0b20023 AMDGPU/GlobalISel: Add copyCost for VGPR->SGPR copies
Patch by Tom Stellard

llvm-svn: 326467
2018-03-01 19:09:25 +00:00
Matt Arsenault
3f6a204eaa AMDGPU/GlobalISel: Make i32 xor legal
llvm-svn: 326466
2018-03-01 19:09:21 +00:00
Matt Arsenault
8e80a5fbca AMDGPU/GlobalISel: Mark 32/64-bit G_FCMP as legal
Patch by Tom Stellard

llvm-svn: 326465
2018-03-01 19:09:16 +00:00
Matt Arsenault
dd022ce064 AMDGPU/GlobalISel: Mark 32-bit G_FPTOSI as legal
Patch by Tom Stellard

llvm-svn: 326464
2018-03-01 19:04:25 +00:00
Ed Maste
9a289f7b72 Correct man page description for --section-start
The argument is section=address, not just address.

(For compatibility with GNU linkers we need to, but do not yet, accept
--section-start=section=address.)

llvm-svn: 326463
2018-03-01 19:02:41 +00:00
Artem Dergachev
61199443fe [analyzer] Enable cfg-temporary-dtors by default.
Don't enable c++-temp-dtor-inlining by default yet, due to this reference
counting pointe problem.

Otherwise the new mode seems stable and allows us to incrementally fix C++
problems in much less hacky ways.

Differential Revision: https://reviews.llvm.org/D43804

llvm-svn: 326461
2018-03-01 18:53:13 +00:00
Sam Clegg
503fdea3cb [WebAssembly] Fix broken gcc build after rL326454
The gcc builders were broken by rL326454
See: https://reviews.llvm.org/D43921

llvm-svn: 326460
2018-03-01 18:48:08 +00:00
Ed Maste
dde3a9170c Where possible use --long-opt=value in lld man page
We intend to maintain compatibility with GNU ld, and in the GNU world
long options are conventionally specified as --long-option=value. For
whatever reason GNU ld.bfd accepts both --long-option value and
--long-option=value, but documents the former. Follow suit.

Some lld long options do not accept the = form; this is probably a bug
to be fixed (along with a man page update).

Reported by Ingo Schwarze, for --entry.

llvm-svn: 326459
2018-03-01 18:40:11 +00:00
Eric Liu
39195e64e2 [clangd] Make symbol name a required parameter for CanonicalIncludes::mapHeader
llvm-svn: 326458
2018-03-01 18:30:48 +00:00
Artem Belevich
8c9749b1dc [NVPTX] use pattern matching to lower int_nvvm_match_all_sync*.
Now that patterns can handle intrinsics returning multiple results,
use tablegen'ed pattern matching instead of custom lowering.

Differential Revision: https://reviews.llvm.org/D43890

llvm-svn: 326457
2018-03-01 18:28:45 +00:00
Eric Liu
b96363da76 [clangd] Support include canonicalization in symbol leve.
Summary:
Symbols with different canonical includes might be defined in the same header
(e.g. symbols defined in STL <iosfwd>). This patch adds support for mapping from
qualified symbol names to canonical headers and special mapping for symbols in <iosfwd>

Reviewers: sammccall, hokein

Reviewed By: sammccall

Subscribers: klimek, ilya-biryukov, jkorous-apple, cfe-commits

Differential Revision: https://reviews.llvm.org/D43869

llvm-svn: 326456
2018-03-01 18:06:40 +00:00
Sam Clegg
8518e7ded5 [WebAssembly] Use uint8_t for single byte values to match the spec
Differential Revision: https://reviews.llvm.org/D43922

llvm-svn: 326455
2018-03-01 18:06:39 +00:00
Sam Clegg
03e101f1b0 [WebAssembly] Use uint8_t for single byte values to match the spec
The original BinaryEncoding.md document used to specify that
these values were `varint7`, but the official spec lists them
explicitly as single byte values and not LEB.

A similar change for wabt is in flight:
 https://github.com/WebAssembly/wabt/pull/782

Differential Revision: https://reviews.llvm.org/D43921

llvm-svn: 326454
2018-03-01 18:06:21 +00:00
Zachary Turner
c6a75a69f1 [PDB] Defer writing the build id until the rest of the PDB is written.
For now this is NFC, but this small refactor opens the door to
letting us embed a hash of the PDB in the build id field of the
PDB.

Differential Revision: https://reviews.llvm.org/D43913

llvm-svn: 326453
2018-03-01 18:00:29 +00:00
Eric Liu
621cef600b [clangd] Forward all environment variables along with CLANGD_TRACE to clangd.
llvm-svn: 326452
2018-03-01 17:42:27 +00:00
Alexander Timofeev
0081d23fd8 [AMDGPU] : fix for the crash in SIRegisterInfo when the regiser class not found
Differential revision: https://reviews.llvm.org./D43334

llvm-svn: 326451
2018-03-01 17:36:43 +00:00
Krzysztof Parzyszek
22a21d4c5d [Hexagon] Add guest registers
llvm-svn: 326450
2018-03-01 17:03:26 +00:00
Pavel Labath
e1463ef4d3 Make TestDynamicValueSameBase gcc-compatible
gcc will say that the type of "this" is "T * const", clang "T *".
Compare the unqualified type names to erase the difference between the
two, as the constness is not a part of this test.

FWIW, I think that the gcc behavior makes more sense here.

llvm-svn: 326449
2018-03-01 16:56:28 +00:00
Sanjay Patel
d696e93cb6 [InstCombine] remove stale comments for tests; NFC
llvm-svn: 326448
2018-03-01 16:28:32 +00:00
Stefan Pintilie
e894e0ff6f [Power9] Add missing instructions to the Power 9 scheduler
Adding more instructions using InstRW so that we can move away from ItinRW
and ultimately have a complete Power 9 scheduler.

Differential Revision: https://reviews.llvm.org/D43899

llvm-svn: 326447
2018-03-01 16:16:08 +00:00
Ed Maste
a83e226c2f Correct markup and nits in ld.lld man page
Patch by Ingo Schwarze

llvm-svn: 326446
2018-03-01 16:02:19 +00:00
Nicholas Wilson
f6be8e8c57 [WebAssembly] Update pre-generated test files to match latest llc output. NFC.
The ordering of llc's output was changed in rL326334.

Differential Revision: https://reviews.llvm.org/D43941

llvm-svn: 326445
2018-03-01 15:55:59 +00:00
Sanjay Patel
f3b1af7aa4 [InstCombine] simplify code for (X*Y) * X => (X*X) * Y ; NFCI
llvm-svn: 326444
2018-03-01 15:50:26 +00:00
Sebastian Pop
c33af715d7 [AArch64] generate vuzp instead of mov
when a BUILD_VECTOR is created out of a sequence of EXTRACT_VECTOR_ELT with a
specific pattern sequence, either <0, 2, 4, ...> or <1, 3, 5, ...>, replace the
BUILD_VECTOR with either vuzp1 or vuzp2.

With this patch LLVM generates the following code for the first function fun1 in the testcase:
adrp x8, .LCPI0_0
ldr  q0, [x8, :lo12:.LCPI0_0]
tbl  v0.16b, { v0.16b }, v0.16b
ext  v1.16b, v0.16b, v0.16b, #8
uzp1 v0.8b, v0.8b, v1.8b
str  d0, [x8]
ret

Without this patch LLVM currently generates this code:
adrp    x8, .LCPI0_0
ldr     q0, [x8, :lo12:.LCPI0_0]
tbl     v0.16b, { v0.16b }, v0.16b
mov     v1.16b, v0.16b
mov     v1.b[1], v0.b[2]
mov     v1.b[2], v0.b[4]
mov     v1.b[3], v0.b[6]
mov     v1.b[4], v0.b[8]
mov     v1.b[5], v0.b[10]
mov     v1.b[6], v0.b[12]
mov     v1.b[7], v0.b[14]
str     d1, [x8]
ret

llvm-svn: 326443
2018-03-01 15:47:39 +00:00
Sanjay Patel
3fd43a843b [InstCombine] move/add tests for fmul reassociation; NFC
This transform may be out-of-scope for instcombine, 
but this is only documenting the current behavior.

llvm-svn: 326442
2018-03-01 15:30:44 +00:00
Rafael Espindola
e75b42ee4e Don't allocate a header bellow address 0.
With the current code if the script has a PHDRS we always obey and try
to allocate a header. This can cause Min - HeaderSize to underflow.

It looks like bfd actually prints an error for this case. With this
patch we do the same.

Found while looking at pr36515.

llvm-svn: 326441
2018-03-01 15:25:46 +00:00
Sanjay Patel
237e52674f [InstCombine] auto-generate full checks; NFC
llvm-svn: 326440
2018-03-01 15:13:42 +00:00
Ilya Biryukov
8b9b3bd07c Resubmit [analyzer] Support for naive cross translation unit analysis
Originally submitted as r326323 and r326324.
Reverted in r326432.

Reverting the commit was a mistake.
The breakage was due to invalid build files in our internal buildsystem,
CMakeLists did not have any cyclic dependencies.

llvm-svn: 326439
2018-03-01 14:54:16 +00:00
Hans Wennborg
1bab70109b UsersManual: improve the clang-cl text some more
llvm-svn: 326438
2018-03-01 14:48:19 +00:00
Tatyana Krasnukha
0a6b8b6630 Make Finalize tolerant of empty register sets.
llvm-svn: 326437
2018-03-01 14:36:42 +00:00
Alexey Bataev
d7c6fdbcd5 Revert "[DEBUGINFO] Add flag for DWARF2 or less to use sections as references."
This reverts commit r326328 to remove checks for emission of certain
sections after discussion with Eric Christofer.

llvm-svn: 326436
2018-03-01 14:32:37 +00:00
Jonas Hahnfeld
b0f051ae63 [OMPT] Fix interoperability test with GCC
We have to ensure that the runtime is initialized _before_ waiting
for the two started threads to guarantee that the master threads
post their ompt_event_thread_begin before the worker threads. This
is not guaranteed in the parallel region where one worker thread
could start before the other master thread has invoked the callback.

The problem did not happen with Clang becauses the generated code
calls __kmpc_global_thread_num() and cashes its result for functions
that contain OpenMP pragmas.

Differential Revision: https://reviews.llvm.org/D43882

llvm-svn: 326435
2018-03-01 14:03:18 +00:00
Hans Wennborg
69d6d7a4d8 UsersManual: beef up the clang-cl text a little
llvm-svn: 326434
2018-03-01 14:00:19 +00:00
Than McIntosh
b3d88a7466 [CodeGen] fix argument attribute in lowering statepoint/patchpoint
Summary:
Use the correct loop index varaible, ArgI, to retrieve attributes.

Reviewers: thanm, sanjoy, rnk

Reviewed By: rnk

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D43832

llvm-svn: 326433
2018-03-01 13:31:57 +00:00