5 Commits

Author SHA1 Message Date
Fangrui Song
de9d80c1c5 [llvm] LLVM_FALLTHROUGH => [[fallthrough]]. NFC
With C++17 there is no Clang pedantic warning or MSVC C5051.
2022-08-08 11:24:15 -07:00
zhongyunde
bddf20735e [AArch64][NFC] Set true for default of subfeature is more readable
Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D129960
2022-07-19 09:00:00 +08:00
zhongyunde
0cb33551ec [AArch64][NFC] Fix a comment error
Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D127708
2022-06-14 13:57:41 +08:00
zhongyunde
c42a225545 [MachineScheduler] Order more stores by ascending address
According D125377, we order STP Q's by ascending address. While on some
targets, paired 128 bit loads and stores are slow, so the STP will split
into STRQ and STUR, so I hope these stores will also be ordered.
Also add subtarget feature ascend-store-address to control the aggressive order.

Reviewed By: dmgreen, fhahn

Differential Revision: https://reviews.llvm.org/D126700
2022-06-13 17:33:50 +08:00
Andre Vieira
572fc7d2fd [AArch64] Order STP Q's by ascending address
This patch adds an AArch64 specific PostRA MachineScheduler to try to schedule
STP Q's to the same base-address in ascending order of offsets. We have found
this to improve performance on Neoverse N1 and should not hurt other AArch64
cores.

Differential Revision: https://reviews.llvm.org/D125377
2022-05-23 09:50:44 +01:00