3 Commits

Author SHA1 Message Date
Matt Arsenault
cc5a1b3dd9 llvm-reduce: Add cloning of target MachineFunctionInfo
MIR support is totally unusable for AMDGPU without this, since the set
of reserved registers is set from fields here.

Add a clone method to MachineFunctionInfo. This is a subtle variant of
the copy constructor that is required if there are any MIR constructs
that use pointers. Specifically, at minimum fields that reference
MachineBasicBlocks or the MachineFunction need to be adjusted to the
values in the new function.
2022-06-07 10:14:48 -04:00
Jim Lin
6bf22ae4d3 [M68k][NFC] Fix file header
Let all file header have the same style. NFC.
2022-01-04 10:14:01 +08:00
Min-Yih Hsu
5ac19e0acf [M68k](5/8) Target-specific lowering
- TargetMachine implementation for M68k
 - ISel, ISched for M68k
 - Other lowering (e.g. FrameLowering)
 - AsmPrinter

Authors: myhsu, m4yers, glaubitz

Differential Revision: https://reviews.llvm.org/D88391
2021-03-08 12:30:57 -08:00