7 Commits

Author SHA1 Message Date
David Green
c782e3497d [AArch64] Add VSHL knownBits handling.
These can be handled in the same way as other shifts.
2023-08-08 21:59:53 +01:00
chenglin.bi
57a366be1e [DAGCombiner] Update test comments for pr59898; NFC 2023-01-11 10:57:54 +08:00
chenglin.bi
be7d0d6db5 [DAGCombiner] Fix issue with rot chain pattern
faa35fc87370 fix the case of negative input shift. But when `c1`, `c2` is not the same side, it will also cause negative shift amount.
And that negative shift amount can't normalize by urem. So add one more bit size to normalize the last shift amount.

Fix: https://github.com/llvm/llvm-project/issues/59898

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D141363
2023-01-11 01:29:09 +08:00
Simon Pilgrim
f21a754915 [AArch64] Add Issue #59898 test case for D141363 2023-01-10 10:49:29 +00:00
Simon Pilgrim
740d2f6b87 [AArch64] Regenerate rotate.ll test
Simplifies diff for D141363
2023-01-10 10:44:32 +00:00
Nikita Popov
5ddce70ef0 [AArch64] Convert some tests to opaque pointers (NFC) 2022-12-19 12:36:19 +01:00
Charlie Turner
458e79b814 [ARM] Expand ROTL and ROTR of vector value types
Summary: After D13851 landed, we saw backend crashes when compiling the reduced test case included in this patch. The right fix seems to be to allow these vector types for expansion in instruction selection.

Reviewers: rengolin, t.p.northover

Subscribers: RKSimon, t.p.northover, aemerson, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D14082

llvm-svn: 251401
2015-10-27 10:25:20 +00:00