3 Commits

Author	SHA1	Message	Date
Chen Zheng	bc5c637376	enable P10 vector builtins test on AIX 64 bit; NFC ... Verify that P10 vector builtins with type `vector signed __int128` and `vector unsigned __int128` work well on AIX 64 bit.	2022-07-21 04:23:02 -04:00
Albion Fung	d7eb917a7c	[PowerPC] Implementation of 128-bit Binary Vector Mod and Sign Extend builtins ... This patch implements 128-bit Binary Vector Mod and Sign Extend builtins for PowerPC10. Differential: https://reviews.llvm.org/D87394#inline-815858	2020-09-23 01:18:14 -05:00
Amy Kwan	1dc1a3fb0c	[PowerPC] Implement low-order Vector Multiply, Modulus and Divide Instructions ... This patch aims to implement the low order vector multiply, divide and modulo instructions available on Power10. The patch involves legalizing the ISD nodes MUL, UDIV, SDIV, UREM and SREM for v2i64 and v4i32 vector types in order to utilize the following instructions: - Vector Multiply Low Doubleword: vmulld - Vector Modulus Word/Doubleword: vmodsw, vmoduw, vmodsd, vmodud - Vector Divide Word/Doubleword: vdivsw, vdivsd, vdivuw, vdivud Differential Revision: https://reviews.llvm.org/D82510	2020-07-23 17:18:36 -05:00