3 Commits

Author SHA1 Message Date
Eric Biggers
09058654f6
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
The RISC-V vector crypto extensions have been ratified. This patch
updates the Clang and LLVM support for these extensions to be
non-experimental, while leaving the C intrinsics as experimental since
the C intrinsics are not yet standardized.

Co-authored-by: Brandon Wu <brandon.wu@sifive.com>
2023-12-18 22:04:22 -08:00
Luke Lau
3a4ad45a2c [DAGCombiner] Combine trunc (splat_vector x) -> splat_vector (trunc x)
From the discussion in https://reviews.llvm.org/D158853, moving the truncate
into the splat helps more splatted scalar operands get selected on RISC-V, and
also avoids the need for splat_vector_parts on RV32.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D159147
2023-08-30 15:22:57 +01:00
Luke Lau
33a93a41df [RISCV] Add SDNode patterns for vwsll.[vv,vx,vi]
This reuses the patterns introduced to help lower vnsr[a,l].vx in D155698.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D155936
2023-07-26 20:26:35 +01:00