484696 Commits

Author SHA1 Message Date
Ilya Biryukov
95b423e44f [Sema] NFC. Simplify code in a few places of TryOrBuildParenListInitialization 2023-12-22 12:41:52 +01:00
Dominik Adamski
ffabf73553
[NFC][OpenMP][MLIR] Add test for lowering parallel workshare GPU loop (#76144)
This test checks if MLIR code is lowered according to schema presented
below:

func1() {
    call __kmpc_parallel_51(..., func2, ...)
}

func2() {
   call __kmpc_for_static_loop_4u(..., func3, ...)
}

func3() {
   //loop body
}
2023-12-22 11:58:04 +01:00
Nikita Popov
c16559137c [IndVars] Avoid unnecessary truncate for zext nneg use
When performing sext IV widening, if one of the narrow uses is in
a zext nneg, we can treat it like an sext and avoid the insertion
of a trunc.
2023-12-22 11:30:17 +01:00
Nikita Popov
24e80d4cc5 [IndVars] Move "using namespace" to top-level scope (NFC) 2023-12-22 11:28:54 +01:00
Matt Arsenault
f7c3627338
DAG: Implement promotion for strict_fpextend (#74310)
Test is a placeholder, will be merged into the existing test after
additional bug fixes for illegal f16 targets are fixed.
2023-12-22 17:15:52 +07:00
Qizhi Hu
625197d39c
[clang][ASTImporter] Support Importer of BuiltinBitCastExpr (#74813)
Since import `ExplicitCastExpr` lacks of processing
`BuiltinBitCastExprClass` type, it would reach to the 'unreachable' code
and produce the crash. This patch aims to fix the
[crash](https://github.com/llvm/llvm-project/issues/74774) and try to
handle `BuiltinBitCastExpr`.

Co-authored-by: huqizhi <836744285@qq.com>
2023-12-22 18:06:59 +08:00
Lucas Duarte Prates
7109a462cd
[AArch64] Assembly support for the Armv9.5-A RAS Extensions (#76161)
This implements assembly support for the RAS extensions introduced as
part of the Armv9.5-A architecture version.
The changes include:
* New system registers for Delegated SError exceptions for EL3
(FEAT_E3DSE):
  * VDISR_EL3
  * VSESR_EL3

Mode details about these extensions can be found at:
* https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2023
* https://developer.arm.com/documentation/ddi0602/2023-09/

Co-authored-by: Jirui Wu <jirui.wu@arm.com>
Co-authored-by: Oliver Stannard <oliver.stannard@arm.com>
2023-12-22 10:06:06 +00:00
jeanPerier
0ac1dfa311
[flang] lower c_f_procpointer (#76071)
This is equivalent to a procedure pointer assignment, except that the
target is a C_FUNPTR.
2023-12-22 11:01:03 +01:00
jeanPerier
30a1c0aa27
[flang] c_funloc - handle pocedure pointers in convertToBox (#76070)
C_FUNLOC was not handling procedure pointer argument correctly, the
issue lied in `hlfir::convertToBox` that did not handle procedure
pointers.

I modified the interface of `hlfir::convertToXXX` to take values on the
way because hlfir::Entity are fundamentally an mlir::Value with type
guarantees, so they should be dealt with by value as mlir::Value are
(they are very small).
2023-12-22 10:59:59 +01:00
jeanPerier
f3fa603d74
[flang] lower ASSOCIATED for procedure pointers (#76067)
This is a lot less complex than the data case where the shape has to be
accounted for, so the implementation is done inline.

One corner case will not be supported correctly for now: the case where
POINTER and TARGET points to the same internal procedure may return
false because lowering is creating fir.embox_proc each time the address
of an internal procedure is taken, so different thunk for the same
internal procedure/host link may be created and compare to false. This
will be fixed in a later patch that moves creating of internal procedure
fir.embox_proc in the host so that the addresses are the same when the
host link is the same. This change is required to properly support the
required lifetime of internal procedure addresses anyway (should be the
always be the lifetime of the host, even when the address is taken in an
internal procedure).
2023-12-22 10:59:01 +01:00
Matt Arsenault
0e46b49de4 Reapply "RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG"
This reverts commit c398fa009a47eb24f88383d5e911e59e70f8db86.

PPC backend was fixed in 2f82662ce901c6666fceb9c6c5e0de216a1c9667
2023-12-22 16:46:22 +07:00
Nikita Popov
54067c5fbe [SROA] Use memcpy if type size does not match store size
The original memcpy also copies the padding, so make sure that
this is still the case after splitting.

Fixes https://github.com/llvm/llvm-project/issues/64081.
2023-12-22 10:19:22 +01:00
Nikita Popov
3f199cb14c [SROA] Add test for #64081 (NFC) 2023-12-22 10:19:21 +01:00
Balázs Kéri
0d903b689a
[clang][ASTImporter] Import AlignValueAttr correctly. (#75308)
Expression of attribute `align_value` was not imported. Import of the
attribute is corrected, a test for it is added, other related tests with
FIXME are updated.
Fixes #75054.
2023-12-22 10:07:38 +01:00
Wang Pengcheng
17858ce6f3
[MacroFusion] Remove createBranchMacroFusionDAGMutation (#76209)
Instead, we add a `BranchOnly` parameter to indicate that only
branches with its predecessors will be fused.

X86 is the only user of `createBranchMacroFusionDAGMutation`.
2023-12-22 16:31:38 +08:00
Shan Huang
06a9c6738a
[CVP] Fix #76058: missing debug location in processSDiv function (#76118)
This PR fixes #76058.
2023-12-22 09:26:32 +01:00
Shengchen Kan
ff32ab3ae7 [X86][NFC] Not imply TB in PS|PD|XS|XD
This can help us aovid introducing new classes T_MAP*PS|PD|XS|XD
when a new opcode map is supported.

And, T_MAP*PS|PD|XS|XD does not look better than T_MAP*, PS|PD|XS|XD.
2023-12-22 15:44:30 +08:00
Matthias Springer
73b86d1b2d
[mlir][Transforms] GreedyPatternRewriteDriver: verify IR (#74270)
This commit adds an additional "expensive check" that verifies the IR
before starting a greedy pattern rewriter, after every pattern
application and after every folding. (Only if
`MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS` is set.)

It also adds an assertion that the `scope` region (part of
`GreedyRewriteConfig`) is not being erased as part of the greedy pattern
rewrite. That would break the scoping mechanism and the expensive
checks.

This commit does not fix any patterns, this is done in separate commits.
2023-12-22 16:44:07 +09:00
Aiden Grossman
a15532d764
[X86] Add CPU detection for more znver2 CPUs (#74955)
This patch adds proper detection support for more znver2 CPUs.

Specifically, this adds in support for CPUs codenamed Renoir, Lucienne,
and Mendocino.

This was originally proposedfor Renoir in
https://reviews.llvm.org/D96220 and
got approved, but slipped through the cracks. However, there is still a
demand for this feature.

In addition to adding support for more znver2 CPUs, this patch also includes
some additional refactoring and comments related to cpu model
information for zen CPUs.

Fixes https://github.com/llvm/llvm-project/issues/74934.
2023-12-21 23:39:28 -08:00
Ben Shi
e2d0f50cd6 [clang][NFC] Remove trailing whitespace characters 2023-12-22 15:34:13 +08:00
XinWang10
1d4691a233
[X86][MC] Support Enc/Dec for EGPR for promoted CMPCCXADD instruction (#76125)
R16-R31 was added into GPRs in
https://github.com/llvm/llvm-project/pull/70958,
This patch supports the encoding/decoding for promoted CMPCCXADD
instruction in EVEX space.

RFC:
https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4
2023-12-22 15:19:56 +08:00
wangpc
59eebb40fb [RISCV] Fix macro-fusions.mir 2023-12-22 14:49:59 +08:00
Aiden Grossman
fc3eed1bce
[Github] Reformat strings for code format action (#75764)
Before this patch, there was a regression in comment formatting due to
some code formatting in bd3e8eb6e325081bf7cfbe93652aa825de3170e5. This
was fixed in 428660cfb986dd0a59cd2a16972c5f7109080522. Github interprets
a tab before a string as starting code formatting. The message that
indicted the code formatting in a PR had been fixed was refactored to a
python multi-line string, but with a tab in front, causing these
messages to be rendered as code blocks in Github, instead of as
intended. This patch builds upon the original fix to reformat the
strings so that they fit within ~80 character lines and are simpler to
modify in the future, hopefully removing traps like the one that caused
the original issue.
2023-12-21 22:49:04 -08:00
Wang Pengcheng
f9c908862a
[RISCV] Split TuneShiftedZExtFusion (#76032)
We split `TuneShiftedZExtFusion` into three fusions to make them
reusable and match the GCC implementation[1].

The zexth/zextw fusions can be reused by XiangShan[2] and other
commercial processors, but shifted zero extension is not so common.

`macro-fusions-veyron-v1.mir` is renamed so it's not relevant to
specific processor.

References:
[1] https://gcc.gnu.org/pipermail/gcc-patches/2023-November/637303.html
[2] https://xiangshan-doc.readthedocs.io/zh_CN/latest/frontend/decode
2023-12-22 14:37:26 +08:00
wangpc
90f816e61f [RISCV] Rename TuneVeyronFusions to TuneVentanaVeyron
And fusion features are added to processor definition.
2023-12-22 14:29:31 +08:00
Vitaly Buka
f25bcfbb29 [test][hwasan] XFAIL new test which fails for unknown reason 2023-12-21 22:24:40 -08:00
XinWang10
7b3323fffb
[X86][MC] Support Enc/Dec for EGPR for promoted CET instruction (#76023)
R16-R31 was added into GPRs in
https://github.com/llvm/llvm-project/pull/70958,
This patch supports the encoding/decoding for promoted CET instruction
in EVEX space.

RFC:
https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4
2023-12-22 14:11:32 +08:00
Matt Arsenault
4d1cd38c95 DAG: Handle promotion of fcanonicalize
This avoids a regression in a future commit
2023-12-22 12:50:18 +07:00
Artur Pilipenko
782cf12d11 Fix chunk-print-before-all script
After c718336c the output of print-before/print-after was changed.
A semicolon was added before the banner "*** IR Dump ..." and this
change broke chunk-print-before-all script.

This change makes it more resilient to small output format variations.
2023-12-21 21:48:04 -08:00
Vitaly Buka
bb7f8f7938 [test][hwasan] Update another test after #76133 2023-12-21 21:47:06 -08:00
Aiden Grossman
cca63f9a36
[Docs] Remove llvm-objdump man page (#75759)
This patch removes the explicit llvm-objdump man page. By enabling
sphinx man page output with `-DLLVM_ENABLE_SPHINX=ON` and
`-DSPHINX_OUTPUT_MAN=ON`, we can generate man pages for all the llvm
binary utilities from the restructured text documentation. Having an
additional man page upstream increases fragementation and maintenance.
2023-12-21 21:42:41 -08:00
Matt Arsenault
c7952d8860 AMDGPU: Add a few more bfloat codegen tests 2023-12-22 12:31:42 +07:00
Matt Arsenault
50ed3b1ecc AMDGPU: Workaround a divergent return value bug in test 2023-12-22 12:31:42 +07:00
Vitaly Buka
beffa1e1f6 [test][hwasan] Try to fix Android bot
https://lab.llvm.org/buildbot/#/builders/77/builds/33152/steps/21/logs/stdio
2023-12-21 21:14:21 -08:00
Vitaly Buka
0ccc1e7acd Revert "[AArch64] Fold more load.x into load.i with large offset"
Issue #76202

This reverts commit f5687636415969e6d945659a0b78734abdfb0f06.
2023-12-21 21:12:40 -08:00
Matt Arsenault
248fba0cd8 AMDGPU: Remove pointless setOperationAction for xint_to_fp
The legalize action for uint_to_fp/sint_to_fp uses the source integer
type, not the result FP type so setting an action on an FP type does
nothing.
2023-12-22 11:24:35 +07:00
Jakub Kuderski
a03c53c530
[mlir][spirv] Add physical storage buffer extension test. NFC. (#76196)
This test demonstrates how the PhysicalStorageBuffer extension can be
used end-2-end in a spir-v module.

This module has been verified to pass serialization, deserialization,
and validation with spirv-val.
2023-12-21 23:06:26 -05:00
Fangrui Song
26ddf4eee2
[ELF] Change .debug_names tombstone value to UINT32_MAX/UINT64_MAX (#74686)
`clang -g -gpubnames -fdebug-types-section` now emits .debug_names
section with references to local type unit entries defined in COMDAT
.debug_info sections.

```
.section        .debug_info,"G",@progbits,5657452045627120676,comdat
.Ltu_begin0:
...

.section        .debug_names,"",@progbits
...
// DWARF32
.long   .Ltu_begin0                     # Type unit 0
// DWARF64
// .long   .Ltu_begin0                     # Type unit 0
```

When `.Ltu_begin0` is relative to a non-prevailing .debug_info section,
the relocation resolves to 0, which is a valid offset within the
.debug_info section.

```
cat > a.cc <<e
struct A { int x; };
inline A foo() { return {1}; }
int main() { foo(); }
e
cat > b.cc <<e
struct A { int x; };
inline A foo() { return {1}; }
void use() { foo(); }
e
clang++ -g -gpubnames -fdebug-types-section -fuse-ld=lld a.cc b.cc -o old
```
```
% llvm-dwarfdump old
...
  Local Type Unit offsets [
    LocalTU[0]: 0x00000000
  ]
...
  Local Type Unit offsets [
    LocalTU[0]: 0x00000000  // indistinguishable from a valid offset within .debug_info
  ]
```

https://dwarfstd.org/issues/231013.1.html proposes that we use a
tombstone value instead to inform consumers. This patch implements the
idea. The second LocalTU entry will now use 0xffffffff.

https://reviews.llvm.org/D84825 has a TODO that we should switch the
tombstone value for most `.debug_*` sections to UINT64_MAX. We have
postponed the change for more than three years for consumers to migrate.
At some point we shall make the change, so that .debug_names is no long
different from other debug section that is not .debug_loc/.debug_ranges.

Co-authored-by: Alexander Yermolovich <ayermolo@meta.com>
2023-12-21 18:59:11 -08:00
Ryan Holt
847a6f8f0a
[mlir][MemRef] Add runtime bounds checking (#75817)
This change adds (runtime) bounds checks for `memref` ops using the
existing `RuntimeVerifiableOpInterface`. For `memref.load` and
`memref.store`, we check that the indices are in-bounds of the memref's
index space. For `memref.reinterpret_cast` and `memref.subview` we check
that the resulting address space is in-bounds of the input memref's
address space.
2023-12-22 11:49:15 +09:00
Shengchen Kan
62d8ae0a1e [X86][NFC] Remove class (VEX/EVEX/XOP)_4V and add class VVVV
`VEX_4V` does not look simpler than `VEX, VVVV`. It's kind of confusing
b/c classes like `VEX_L`, `VEX_LIG` do not imply `VEX` but it does.

For APX, we have promote EVEX, NDD, NF and NDD_NF instructions. All of
the 4 variants are in EVEX space and NDD/NDD_NF set the VVVV fields.
To extract the common fields (e.g EVEX) into a class and set VVVV
conditionally, we need VVVV to not imply other prefixes.
2023-12-22 10:38:15 +08:00
eric
c03745d23a libc++-infa: Hotfix runner group
The runners-32 group is broken, for reasons...
The easiest fix is to move the jobs to runners-8.
(which needs to be renamed, because they're all actually 30 core
machines)
2023-12-21 21:34:21 -05:00
Matthias Springer
c99670ba51
[mlir][vector] LoadOp/StoreOp: Allow 0-D vectors (#76134)
Similar to `vector.transfer_read`/`vector.transfer_write`, allow 0-D
vectors.

This commit fixes
`mlir/test/Dialect/Vector/vector-transfer-to-vector-load-store.mlir`
when verifying the IR after each pattern (#74270). That test produces a
temporary 0-D load/store op.
2023-12-22 11:12:58 +09:00
Vitaly Buka
7db28dd3f8
[hwasan] Classify stack overflow, and use after scope (#76133)
We can't distinguish UAR and UAS, but by definition
UAR is already UAS.
2023-12-21 17:51:14 -08:00
hstk30-hw
033ec098be
[Clang][Sema] Fix Wswitch-default bad warning in template (#76007)
https://github.com/llvm/llvm-project/pull/73077 added -Wswitch-default
diagnostic but it produced false positives in templates. This PR will
address that. https://github.com/llvm/llvm-project/issues/75943
2023-12-22 09:00:41 +08:00
Vitaly Buka
7c3b67d203
[hwasan] Respect strip_path_prefix printing locals (#76132) 2023-12-21 16:03:06 -08:00
Cyndy Ishida
38eea57e69 [ADT] fix grammatical typo in Twine.h docs, NFC 2023-12-21 14:59:14 -08:00
Martin Storsjö
f70b229e96
[LLDB] Define _BSD_SOURCE globally, to get optreset available in mingw's getopt.h (#76137)
We previously were defining _BSD_SOURCE right before including getopt.h.
However, on mingw-w64, getopt.h is also transitively included by
unistd.h, and unistd.h can be transitively included by many headers
(recently, by some libc++ headers).

Therefore, to be safe, we need to define _BSD_SOURCE before including
any header. Thus do this in CMake.

This fixes https://github.com/llvm/llvm-project/issues/76050.
2023-12-22 00:40:12 +02:00
Craig Topper
e64f5d6305
[RISCV] Replace RISCVISD::VP_MERGE_VL with a new node that has a separate passthru operand. (#75682)
ISD::VP_MERGE treats the false operand as the source for elements past
VL. The vmerge instruction encodes 3 registers and treats the vd
register as the source for the tail.

This patch adds a new ISD opcode that models the tail source explicitly.
During lowering we copy the false operand to this operand.

I think we can merge RISCVISD::VSELECT_VL with this new opcode by using
an UNDEF passthru, but I'll save that for another patch.
2023-12-21 14:34:49 -08:00
Arthur Eubanks
3ca9bcc6cc
[llvm][docs][X86] Mention code model improvements in ReleaseNotes (#76190) 2023-12-21 14:30:43 -08:00
Tacet
82b38e83cf
[ASan][libc++] Optimization of container annotations (#76082)
This commit implements conditional compilation for ASan helper code.

As convey to me by @EricWF, string benchmarks with UBSan have been
experiencing significant performance hit after the commit with ASan
string annotations. This is likely due to the fact that no-op ASan code
is not optimized out with UBSan. To address this issue, this commit
conditionalizes the inclusion of ASan helper function bodies using
`#ifdef` directives. This approach allows us to selectively include only
the ASan code when it's actually required, thereby enhancing
optimizations and improving performance.

While issue was noticed in string benchmarks, I expect same overhead
(just less noticeable) in other containers, therefore `std::vector` and
`std::deque` have same changes.

To see impact of that change run `string.libcxx.out` with UBSan and
`--benchmark_filter=BM_StringAssign` or
`--benchmark_filter=BM_StringConstruct`.
2023-12-21 17:26:10 -05:00