2452 Commits

Author SHA1 Message Date
Renato Golin
9258aa5543 Make global named registers internal variables
llvm-svn: 209289
2014-05-21 10:40:27 +00:00
Eric Christopher
6c553d6240 Remove test. Replacing it with a backend test with the optimized IR.
llvm-svn: 209260
2014-05-21 00:00:01 +00:00
Eric Christopher
bd8652d272 Make this test emit llvm IR rather than assembly.
llvm-svn: 209255
2014-05-20 23:23:51 +00:00
Duncan P. N. Exon Smith
6f782b12aa Fix testcase from r209228
llvm-svn: 209229
2014-05-20 19:20:23 +00:00
Duncan P. N. Exon Smith
d22b97c30b GlobalValue: Testcase for hidden visibility and local linkage
This is a testcase for r209227, a change in LLVM that automatically sets
visibility to default when the linkage is changed to local (rather than
asserting).

What this testcase triggers is hard to reproduce otherwise:  the
`GlobalValue` is created (with non-local linkage), the visibility is set
to hidden, and then the linkage is set to local.

PR19760

llvm-svn: 209228
2014-05-20 19:04:31 +00:00
Peter Collingbourne
41af7c2fdc Implement the flatten attribute.
This is a GNU attribute that causes calls within the attributed function
to be inlined where possible. It is implemented by giving such calls the
alwaysinline attribute.

Differential Revision: http://reviews.llvm.org/D3816

llvm-svn: 209217
2014-05-20 17:12:51 +00:00
Robert Lytton
db8c1cb02c XCore target: sort typestring enum fields alphabetically
llvm-svn: 209196
2014-05-20 07:19:33 +00:00
Adrian Prantl
2dbdd20d37 Demote the "Debug Info Version" module flag to llvm::Module::Warning
behavior on mismatch. The AutoUpgrader will drop incompatible debug info
any way and also emit a warning diagnostic for it.

rdar://problem/16926122

llvm-svn: 209182
2014-05-19 23:40:06 +00:00
Renato Golin
c296d951a7 Using SmallString and correct addr var
llvm-svn: 209180
2014-05-19 23:25:25 +00:00
Renato Golin
156a853ccb Fix usage of string when StringRef was needed
Also adding a variable to the test, so release bots match %1.
This should also calm the gdb buildbot.

.

llvm-svn: 209171
2014-05-19 22:36:19 +00:00
Peter Collingbourne
b4728c12e8 Implement the no_split_stack attribute.
This is a GNU attribute that allows split stacks to be turned off on a
per-function basis.

Differential Revision: http://reviews.llvm.org/D3817

llvm-svn: 209167
2014-05-19 22:14:34 +00:00
Renato Golin
230c5eb4bd Non-allocatable Global Named Register
This patch implements global named registers in Clang, lowering to the just
created intrinsics in LLVM (@llvm.read/write_register). A new type of LValue
had to be created (Register), which just adds support to carry the metadata
node containing the name of the register. Two new methods to emit loads and
stores interoperate with another to emit the named metadata node.

No guarantees are being made and only non-allocatable global variable named
registers are being supported. Local named register support is unchanged.

llvm-svn: 209149
2014-05-19 18:15:42 +00:00
Oliver Stannard
a3afc69b94 ARM: PCS non-compliance when struct is padded to avoid register/stack split, and requires internal padding
When we were padding a struct to avoid splitting it between registers and
the stack, we were throwing away the type which the argument should be coerced
to.

llvm-svn: 209122
2014-05-19 13:10:05 +00:00
Rafael Espindola
b2633b9793 Update for llvm api change.
Now that llvm cannot represent alias cycles, we have to diagnose erros just
before trying to close the cycle. This degrades the errors a bit. The real
solution is what it was before: if we want to provide good errors for these
cases, we have to be able to find a clang level decl given a mangled name
and produce the error from Sema.

llvm-svn: 209008
2014-05-16 19:35:48 +00:00
Hans Wennborg
b0f2f146bb Allow dllimport/dllexport on inline functions and adjust the linkage.
This is a step towards handling these attributes on classes (PR11170).

Differential Revision: http://reviews.llvm.org/D3772

llvm-svn: 208925
2014-05-15 22:07:49 +00:00
Tim Northover
fb33438115 ARM64: update tests now that we print "mov" & "mvn".
llvm-svn: 208875
2014-05-15 12:11:10 +00:00
Tim Northover
0f9355b3b0 AArch64: update test after LLVM CodeGen change
llvm-svn: 208868
2014-05-15 11:21:39 +00:00
Hao Liu
9f9492b657 [ARM64]Fix the bug right shift uint64_t by 64 generates incorrect result.
llvm-svn: 208761
2014-05-14 08:59:30 +00:00
David Blaikie
aabde05da1 DebugInfo: Avoid creating DILexicalScopeFiles when the filename in the current scope has not changed.
This looks like the right way for this check to work, but there is
another semi-obvious bug, I would think: why is CurLoc not zero'd out
between functions? The possibility for it to bleed between them seems
problematic. (& indeed I caused tests to fail when I fixed this a
different way, by setting CurLoc to SourceLocation() and the end of
EmitFunctionEnd... )

The changes to debug-info-blocks.m are due to a mismatch between the
source manager's file naming and CGDebugInfo's default handling when no
-main-file-name is specified. This actually reveals somewhat of a bug in
the debug info when using source files from standard in, too. See the
comment in CGDebugInfo::CreateCompileUnit for more details.

llvm-svn: 208742
2014-05-14 00:29:00 +00:00
Filipe Cabecinhas
e897d7e7c2 Fixed a few tests and moved a comment to its proper place
llvm-svn: 208665
2014-05-13 05:21:11 +00:00
Filipe Cabecinhas
5d289b48b1 Patched clang to emit x86 blends as shufflevectors.
Summary:
Most of the clang header patch by Simon Pilgrim @ SCEE.
Also fixed (or added) clang tests for these intrinsics.

LLVM tests to make sure we get the blend instruction out of these
shufflevectors are at http://reviews.llvm.org/D3600

Reviewers: eli.friedman, craig.topper, rafael

Subscribers: cfe-commits

Differential Revision: http://reviews.llvm.org/D3601

llvm-svn: 208664
2014-05-13 02:37:02 +00:00
Saleem Abdulrasool
8ab3e83efa CodeGen: support dll{ex,im}port on WoA
Add ARM support for dllexport and dllimport attributes.  This is a relatively
conservative change.  The alternative is to entirely drop the architecture
requirement.  The dllimport and dllexport attributes are not restricted to any
architecture, simply to platforms that support this attribute (currently
Windows).

llvm-svn: 208486
2014-05-11 01:31:57 +00:00
James Molloy
6f244b6f78 Reapply r208417 (olista01 'ARM: HFAs must be passed in consecutive registers'). Bots are now pacified.
llvm-svn: 208425
2014-05-09 16:21:39 +00:00
James Molloy
1aa0d5f3b2 Revert r208417 (olista01 'ARM: HFAs must be passed in consecutive registers'). This is a followon commit from r208413 which broke the LLVM bots.
llvm-svn: 208422
2014-05-09 16:17:09 +00:00
Oliver Stannard
19f3b4f2ce ARM: HFAs must be passed in consecutive registers
This is the clang counterpart to 208413, which ensures that Homogeneous
Floating-point Aggregates are passed in consecutive registers on ARM.

llvm-svn: 208417
2014-05-09 15:14:56 +00:00
James Molloy
491cefbe7a When doing int<->ptr coercion for big-endian, calculate the shift amount correctly.
Previously we calculated the shift amount based upon DataLayout::getTypeAllocSizeInBits.
This will only work for legal types - types such as i24 that are created as part of
structs for bitfields will return "32" from that function. Change to using
getTypeSizeInBits.

It turns out that AArch64 didn't run across this problem because it always returned
[1 x i64] as the type for a bitfield, whereas ARM64 returns i64 so goes down this
(better, but wrong) codepath.

llvm-svn: 208231
2014-05-07 17:41:15 +00:00
James Molloy
847501f92e Re-satisfy the bots. Due to a de-sync between my clang and LLVM trees, I didn't notice that the generated BE alignment register is now unnamed and is not called '%align_be'.
llvm-svn: 208217
2014-05-07 14:51:57 +00:00
James Molloy
467be60748 [ARM64-BE] Correctly deal with single element HFAs in varargs.
Just because the first "if" didn't fire, doesn't mean we can not have
an HFA in the "else" clause.

llvm-svn: 208216
2014-05-07 14:45:55 +00:00
Oliver Stannard
39d26c98c5 ARM: Fix assertion caused by passing bitfield struct using ABIArgInfo::getExpandWithPadding
In cases where a struct must, according to the AAPCS, not be split between
general purpose and floating point registers, we use
ABIArgInfo::getExpandWithPadding to add the padding arguments. However,
ExpandWithPadding does not work if the struct contains bitfields, so we
instead must use ABIArgInfo::getDirect.

llvm-svn: 208185
2014-05-07 10:39:12 +00:00
David Blaikie
483a9da598 Reapply: DebugInfo: Emit the definition of enums when the definition preceeds the declaration and initial use.
Reverting r208106 to reapply r208065 with a fix for the regression. The
issue was that the enum tried to be built even if the declaration hadn't
been constructed for debug info - presenting problems for enum templates
and typedefs of enums with names for linkage purposes.

Original commit message:

This regressed a little further 208055 though it was already a little
broken.

While the requiresCompleteType optimization should be implemented here.
Future (possibly near future) work.

llvm-svn: 208114
2014-05-06 18:35:21 +00:00
David Blaikie
29020cc571 Revert "DebugInfo: Emit the definition of enums when the definition preceeds the declaration and initial use."
This is breaking the compiler-rt build. Reverting while I
investigate/fix.

This reverts commit r208065.

llvm-svn: 208106
2014-05-06 17:02:15 +00:00
David Blaikie
57407525fd DebugInfo: Emit the definition of enums when the definition preceeds the declaration and initial use.
This regressed a little further 208055 though it was already a little
broken.

While the requiresCompleteType optimization should be implemented here.
Future (possibly near future) work.

llvm-svn: 208065
2014-05-06 07:33:30 +00:00
Nico Weber
9ef9ca470f Support field references to struct names and c++11 aliases from inline asm.
This is in addition to the existing support for typedefs.

llvm-svn: 208053
2014-05-06 03:13:27 +00:00
Rafael Espindola
502f65ae54 Fix pr19653.
Warn if an alias requests a section other than the aliasee section.

llvm-svn: 207997
2014-05-05 20:21:03 +00:00
Alp Toker
08f6e9ec15 Fix some typos
llvm-svn: 207994
2014-05-05 19:53:42 +00:00
Saleem Abdulrasool
956c2ec532 CodeGen: complete ARM ACLE hint 8.4 support
Add support for the remaining hints from the ACLE.  Although __dbg is listed as
a hint, it is handled different, so it is not covered by this change.

llvm-svn: 207930
2014-05-04 02:52:25 +00:00
Robert Lytton
f80d68847d XCore target: fix bug in dereferencing null pointer.
Also add basic cpp ABI tests where they differ from C ABI output.

llvm-svn: 207834
2014-05-02 09:33:30 +00:00
Robert Lytton
844aeeb15a XCore target: Add TypeString meta data to IR output.
This includes the addition of the virtual function:
	TargetCodeGenInfo::EmitTargetMD()

llvm-svn: 207832
2014-05-02 09:33:20 +00:00
Saleem Abdulrasool
38ed6de3a0 CodeGen: rename __builtin_arm_sevl to __sevl
ACLE adds the __sevl() extension.  Rename the hint from a custom name to the
ACLE specified name.

llvm-svn: 207829
2014-05-02 06:53:57 +00:00
Bradley Smith
4da7dd837d [ARM64] Port remaining relevant AArch64 clang tests over to ARM64
llvm-svn: 207632
2014-04-30 10:52:05 +00:00
Hao Liu
a19a2e2da6 [ARM64]Fix a bug cannot select UQSHL/SQSHL with constant i64 shift amount.
llvm-svn: 207401
2014-04-28 07:36:12 +00:00
Saleem Abdulrasool
b9f07e3dbc CodeGen: add __yield intrinsic for ARM
The __yield intrinsic generates a hint instruction to indicate that the thread
is not performing any useful operations at the moment.  This is for
compatibility with MSVC, although, the intrinsic is also part of the ACLE, and
is enabled globally as a result.

llvm-svn: 207275
2014-04-25 21:13:29 +00:00
Benjamin Kramer
1adc8c3391 Print detailed vector type information on diagnostics.
We never aka vector types because our attributed syntax for it is less
comprehensible than the typedefs. This leaves the user in the dark when
the typedef isn't named that well.

Example:
  v2s v; v4f w;
  w = v;

The naming in this cases isn't even that bad, but the error we give is
useless without looking up the actual typedefs.
t.c:6:5: error: assigning to 'v4f' from incompatible type 'v2s'

Now:
t.c:6:5: error: assigning to 'v4f' (vector of 4 'float' values) from
    incompatible type 'v2s' (vector of 2 'int' values)

We do this for all diagnostics that print a vector type.

llvm-svn: 207267
2014-04-25 20:41:38 +00:00
Saleem Abdulrasool
0fd930e86c CodeGen: replace use of @llvm.arm.sevl with @llvm.arm.hint
Use the new generic @llvm.arm.hint hint intrinsic rather than the specialised
@llvm.arm.sevl hint instruction.

llvm-svn: 207243
2014-04-25 17:25:46 +00:00
Andrea Di Biagio
7ceec07cf6 [X86] Add Clang support for intrinsics __rdtsc and __rdtscp.
This patch:
 1. Adds a definition for two new GCCBuiltins in BuiltinsX86.def:
   __builtin_ia32_rdtsc;
   __builtin_ia32_rdtscp;

 2. Replaces the already existing definition of intrinsic __rdtsc in
    ia32intrin.h with a simple call to the new GCC builtin __builtin_ia32_rdtsc.

 3. Adds a definition for the new intrinsic __rdtscp in ia32intrin.h

llvm-svn: 207132
2014-04-24 18:26:35 +00:00
Daniel Sanders
81ea601b54 [mips] Support 128-bit int in N32 ABI by overriding TargetInfo::hasInt128Type()
Summary: The condition in the base class is rather strange. It says a target has the 128-bit integer type if the size of a pointer is >= 64-bits. N32 has 32-bit pointers but 64-bit integers. I'm a bit reluctant to change this for all targets so this patch makes the method virtual and overrides it for MIPS64.

Reviewers: atanasyan

Reviewed By: atanasyan

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D3472

llvm-svn: 207121
2014-04-24 16:05:26 +00:00
Tim Northover
f4aee52345 AArch64: update tests to new way of printing NEON lists.
llvm-svn: 207117
2014-04-24 14:06:31 +00:00
Michael J. Spencer
807cf41e2f Fix test to not depend on llvm optimizations.
llvm-svn: 207062
2014-04-24 02:16:29 +00:00
James Molloy
3a9a023eb6 [ARM64] Enable more CodeGen tests for ARM64. The crypto and neon intrinsics tests needed changing slightly due to the naming differences between AArch64 and ARM64.
llvm-svn: 206964
2014-04-23 10:26:23 +00:00
James Molloy
8bdd24b1a9 [ARM64] Change inline assembly constraints to be more lax, to match the behaviour of Clang/AArch64 and GCC.
GCC allows sub-64bit values to use the 'r' register constraint.

llvm-svn: 206963
2014-04-23 10:26:19 +00:00