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Author SHA1 Message Date
Jim Grosbach
0fba6d98fc ARM64: [su]xtw use W regs as inputs, not X regs. 
Update the SXT[BHW]/UXTW instruction aliases and the shifted reg addressing
mode handling.

PR19455 and rdar://16650642

llvm-svn: 206495
 2014-04-17 20:47:31 +00:00
Tim Northover
00ed9964c6 ARM64: initial backend import 
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.

Everything will be easier with the target in-tree though, hence this
commit.

llvm-svn: 205090
 2014-03-29 10:18:08 +00:00