4 Commits

Author	SHA1	Message	Date
Piotr Sobczak	4067de569f	[AMDGPU] Select s_cselect ... Summary: Add patterns to select s_cselect in the isel. Handle more cases of implicit SCC accesses in si-fix-sgpr-copies to allow new patterns to work. Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, asbirlea, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D81925	2020-06-19 16:17:46 +02:00
Stanislav Mekhanoshin	71ed66d97f	[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal ... We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808	2020-05-12 16:05:12 -07:00
Stanislav Mekhanoshin	310d32cb80	[AMDGPU] Fix promote alloca which is already vector ... Just do not touch loads and stores which are already vector. Previously pass was just unable to see these loads and stores because these were hidden bitcasts. Differential Revision: https://reviews.llvm.org/D79738	2020-05-11 14:52:31 -07:00
Stanislav Mekhanoshin	db7dea2b6f	[AMDGPU] Vectorize alloca thru bitcast ... This is mostly useful if alloca element type is not integer and then casted to an integer for load or store. We now can vectorize an [i32] alloca but cannot do so for [float]. There also a separate patch needed to properly lower 64 bit types after they vectorized. At the moment these are lowered via scratch anyway. Differential Revision: https://reviews.llvm.org/D79641	2020-05-08 15:11:38 -07:00