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88 Commits

Author SHA1 Message Date
Torok Edwin
69208f0f9e Remove extra \n from LLVM_UNREACHABLE calls. 
llvm-svn: 75416
 2009-07-12 07:15:17 +00:00
Evan Cheng
e3a53c448b Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead. 
llvm-svn: 75048
 2009-07-08 21:03:57 +00:00
Torok Edwin
fb8d6d5b58 Implement changes from Chris's feedback. 
Finish converting lib/Target.

llvm-svn: 75043
 2009-07-08 20:53:28 +00:00
Torok Edwin
6dd2730024 Start converting to new error handling API. 
cerr+abort -> llvm_report_error
assert(0)+abort -> LLVM_UNREACHABLE (assert(0)+llvm_unreachable-> abort() included)

llvm-svn: 75018
 2009-07-08 18:01:40 +00:00
Evan Cheng
b61e3a83ee Add a todo. 
llvm-svn: 74976
 2009-07-08 00:05:05 +00:00
Evan Cheng
2cff076cfe Statically encode bit 25 to indicate immediate form of data processing instructions. Patch by Sean Callanan. 
llvm-svn: 74972
 2009-07-07 23:40:25 +00:00
Evan Cheng
40398233b7 Add bfc to armv6t2. 
llvm-svn: 74868
 2009-07-06 22:23:46 +00:00
Bruno Cardoso Lopes
5661ea68e7 Add the Object Code Emitter class. Original patch by Aaron Gray, I did some 
cleanup, removed some #includes and moved Object Code Emitter out-of-line.

llvm-svn: 74813
 2009-07-06 05:09:34 +00:00
David Goodwin
28d6d87244 Improve Thumb-2 jump table support. 
llvm-svn: 74549
 2009-06-30 19:50:22 +00:00
Anton Korobeynikov
99152f3a2c Split thumb-related stuff into separate classes. 
Step 1: ARMInstructionInfo => {ARM,Thumb}InstructionInfo

llvm-svn: 74329
 2009-06-26 21:28:53 +00:00
Evan Cheng
1283c6a066 Part 1. 
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.

Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0

If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.

- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.

This is work in progress, not yet enabled.

llvm-svn: 73381
 2009-06-15 08:28:29 +00:00
Bruno Cardoso Lopes
9fd794bebf Fix new CodeEmitter stuff to follow LLVM codying style. Patch by Aaron Gray 
llvm-svn: 72697
 2009-06-01 19:57:37 +00:00
Bruno Cardoso Lopes
a194c3a69e First patch in the direction of splitting MachineCodeEmitter in two subclasses: 
JITCodeEmitter and ObjectCodeEmitter. No functional changes yet. Patch by Aaron Gray

llvm-svn: 72631
 2009-05-30 20:51:52 +00:00
Evan Cheng
0b77319742 Fix MachineCodeEmitter to use uintptr_t instead of intptr_t. This avoids some overflow issues. Patch by Thomas Jablin. 
llvm-svn: 60828
 2008-12-10 02:32:19 +00:00
Evan Cheng
5f23e9fe73 Fix a thinko. MO is getOperand(i-1) so we don't have to adjust e. 
llvm-svn: 59696
 2008-11-20 02:25:51 +00:00
Evan Cheng
59213d64e5 Eliminate a compile time warning. 
llvm-svn: 59678
 2008-11-19 23:21:33 +00:00
Evan Cheng
30f6f8fdad Fix MOVrx, MOVsrl_flag, and MOVsra_flag encodings. 
llvm-svn: 59314
 2008-11-14 20:09:11 +00:00
Evan Cheng
fabdcce677 Handle the rest of pseudo instructions. 
llvm-svn: 59275
 2008-11-13 23:36:57 +00:00
Evan Cheng
935963de81 Don't forget to emit stubs for function GV's emitted in CONSTPOOL_ENTRY's. 
llvm-svn: 59258
 2008-11-13 19:22:28 +00:00
Evan Cheng
4af89f7e7d Missed a break statement. 
llvm-svn: 59231
 2008-11-13 07:46:59 +00:00
Evan Cheng
2666f59322 Fix pre- and post-indexed load / store encoding bugs. 
llvm-svn: 59230
 2008-11-13 07:34:59 +00:00
Evan Cheng
45d030a05a Address mode immediate offset has already been divided by 4. 
llvm-svn: 59117
 2008-11-12 08:21:12 +00:00
Evan Cheng
052f20d3b1 Fix a VFP binary arithmetic instruction encoding bug. 
llvm-svn: 59116
 2008-11-12 08:14:21 +00:00
Evan Cheng
2836d91630 Fix address mode 3 immediate offset mode encoding. 
llvm-svn: 59109
 2008-11-12 07:34:37 +00:00
Evan Cheng
af644b50b4 Consolidate formats; fix FCMPED etc. encodings. 
llvm-svn: 59107
 2008-11-12 07:18:38 +00:00
Evan Cheng
4b6c7efbde Fix VFP conversion instruction encodings. 
llvm-svn: 59104
 2008-11-12 06:41:41 +00:00
Evan Cheng
a0e2f26320 Fix encoding of single-precision VFP registers. 
llvm-svn: 59102
 2008-11-12 02:19:38 +00:00
Evan Cheng
bfcee5b863 VFP fld / fst immediate field is multiplied by 4. 
llvm-svn: 59100
 2008-11-12 01:02:24 +00:00
Evan Cheng
97ccab888a Fix FMDRR encoding. 
llvm-svn: 59088
 2008-11-11 22:46:12 +00:00
Evan Cheng
ad519bbe54 Handle floating point constpool_entry's. 
llvm-svn: 59087
 2008-11-11 22:19:31 +00:00
Evan Cheng
8cbbcb1f2f Encode VFP load / store instructions. 
llvm-svn: 59084
 2008-11-11 21:48:44 +00:00
Evan Cheng
38c9a14a88 Encode VFP conversion instructions. 
llvm-svn: 59074
 2008-11-11 19:40:26 +00:00
Evan Cheng
ac2af2fdb2 Encode VFP arithmetic instructions. 
llvm-svn: 59016
 2008-11-11 02:11:05 +00:00
Evan Cheng
9f3058f3be Rename isGVNonLazyPtr to isIndirectSym to reflect how it will be used. 
llvm-svn: 58949
 2008-11-10 01:08:07 +00:00
Evan Cheng
98161f5f34 Tell ARMJITInfo if codegen relocation is PIC. It changes how function stubs are generated. 
llvm-svn: 58896
 2008-11-08 07:38:22 +00:00
Evan Cheng
bb373c4637 Fix relocation for calls to external symbols. 
llvm-svn: 58893
 2008-11-08 07:22:33 +00:00
Evan Cheng
077c8f8832 Skip over two-address use operands. 
llvm-svn: 58883
 2008-11-08 01:44:13 +00:00
Evan Cheng
ffdd91e3b8 Handle ARM machine constantpool entry with non-lazy ptr. 
llvm-svn: 58882
 2008-11-08 01:31:27 +00:00
Evan Cheng
ef4d78ba67 More code clean up. 
llvm-svn: 58872
 2008-11-07 22:57:53 +00:00
Evan Cheng
8467e2459a Get PIC jump table working. 
llvm-svn: 58869
 2008-11-07 22:30:53 +00:00
Evan Cheng
7095cd2af2 Jump table JIT support. Work in progress. 
llvm-svn: 58836
 2008-11-07 09:06:08 +00:00
Evan Cheng
98dc53e926 Encode misc arithmetic instructions. 
llvm-svn: 58828
 2008-11-07 01:41:35 +00:00
Evan Cheng
49d665218c Encode extend instructions; more clean up. 
llvm-svn: 58818
 2008-11-06 22:15:19 +00:00
Evan Cheng
aa03cd3336 - Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm. 
- Consolidate instruction formats.
- Other clean up.

llvm-svn: 58808
 2008-11-06 17:48:05 +00:00
Evan Cheng
47b546d75f Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug. 
llvm-svn: 58800
 2008-11-06 08:47:38 +00:00
Evan Cheng
b870fd8874 Fix so_imm encoding bug; add support for MOVi2pieces. 
llvm-svn: 58790
 2008-11-06 02:25:39 +00:00
Evan Cheng
2686c8fb34 Fix encoding of multiple instructions with 3 src operands; also handle smmul, smmla, and smmls. 
llvm-svn: 58789
 2008-11-06 01:21:28 +00:00
Evan Cheng
fd2adbfa28 Encode pic load / store instructions; fix some encoding bugs. 
llvm-svn: 58780
 2008-11-05 23:22:34 +00:00
Evan Cheng
81889d010c Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions. 
llvm-svn: 58764
 2008-11-05 18:35:52 +00:00
Evan Cheng
4eaff40147 Debug output tweak. 
llvm-svn: 58708
 2008-11-04 17:58:53 +00:00