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108 Commits

Author SHA1 Message Date
David Goodwin
03ab0bbb24 Generalize opcode selection in ARMBaseRegisterInfo. 
llvm-svn: 75036
 2009-07-08 20:28:28 +00:00
David Goodwin
af7451b674 Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first. 
llvm-svn: 75010
 2009-07-08 16:09:28 +00:00
David Goodwin
ade05a37f1 Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2. 
llvm-svn: 74731
 2009-07-02 22:18:33 +00:00
Evan Cheng
d379e896ff Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details. 
llvm-svn: 74580
 2009-07-01 01:59:31 +00:00
David Goodwin
28d6d87244 Improve Thumb-2 jump table support. 
llvm-svn: 74549
 2009-06-30 19:50:22 +00:00
David Goodwin
27303cde82 Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table. 
llvm-svn: 74543
 2009-06-30 18:04:13 +00:00
Anton Korobeynikov
0f2158b35f Simplify a bit 
llvm-svn: 74385
 2009-06-27 12:59:03 +00:00
Anton Korobeynikov
a1b5b18bd0 ARM refactoring. Step 2: split RegisterInfo 
llvm-svn: 74384
 2009-06-27 12:16:40 +00:00
Anton Korobeynikov
99152f3a2c Split thumb-related stuff into separate classes. 
Step 1: ARMInstructionInfo => {ARM,Thumb}InstructionInfo

llvm-svn: 74329
 2009-06-26 21:28:53 +00:00
Bob Wilson
2e076c4e02 Add support for ARM's Advanced SIMD (NEON) instruction set. 
This is still a work in progress but most of the NEON instruction set
is supported.

llvm-svn: 73919
 2009-06-22 23:27:02 +00:00
Anton Korobeynikov
5d28cb204f GNU as refuses to assemble "pop {}" instruction. Do not emit such 
(this is the case when we have thumb vararg function with single
callee-saved register, which is handled separately).

llvm-svn: 73529
 2009-06-16 18:49:08 +00:00
Jim Grosbach
06928192ae Update the names of the exception handling sjlj instrinsics to 
llvm.eh.sjlj.* for better clarity as to their purpose and scope. Add
a description of llvm.eh.sjlj.setjmp to ExceptionHandling.html.
(llvm.eh.sjlj.longjmp documentation coming when that implementation is
added).

llvm-svn: 71758
 2009-05-14 00:46:35 +00:00
Bill Wendling
f7b83c7ae7 Change MachineInstrBuilder::addReg() to take a flag instead of a list of 
booleans. This gives a better indication of what the "addReg()" is
doing. Remembering what all of those booleans mean isn't easy, especially if you
aren't spending all of your time in that code.

I took Jakob's suggestion and made it illegal to pass in "true" for the
flag. This should hopefully prevent any unintended misuse of this (by reverting
to the old way of using addReg()).

llvm-svn: 71722
 2009-05-13 21:33:08 +00:00
Jim Grosbach
aeca45dd6f Add support for GCC compatible builtin setjmp and longjmp intrinsics. This is 
a supporting preliminary patch for GCC-compatible SjLJ exception handling. Note that these intrinsics are not designed to be invoked directly by the user, but
rather used by the front-end as target hooks for exception handling.

llvm-svn: 71610
 2009-05-12 23:59:14 +00:00
Jim Grosbach
fde2110aa9 PR2985 / <rdar://problem/6584986> 
When compiling in Thumb mode, only the low (R0-R7) registers are available
for most instructions. Breaking the low registers into a new register class
handles this. Uses of R12, SP, etc, are handled explicitly where needed
with copies inserted to move results into low registers where the rest of
the code generator can deal with them.

llvm-svn: 68545
 2009-04-07 20:34:09 +00:00
Bob Wilson
6bedd59894 Wrap some lines to fix indentation problems. 
llvm-svn: 68405
 2009-04-03 21:08:42 +00:00
Bob Wilson
d24b794f31 Fix some comments. 
llvm-svn: 68404
 2009-04-03 20:53:25 +00:00
Dan Gohman
2af1f85f1f Factor out the code to add a MachineOperand to a MachineInstrBuilder. 
llvm-svn: 64891
 2009-02-18 05:45:50 +00:00
Dale Johannesen
7647da67ea Remove refs to non-DebugLoc versions of BuildMI from ARM. 
llvm-svn: 64429
 2009-02-13 02:25:56 +00:00
Dale Johannesen
6b8c76a910 Eliminate a couple of non-DebugLoc BuildMI variants. 
Modify callers.

llvm-svn: 64409
 2009-02-12 23:08:38 +00:00
Bill Wendling
f6d609a227 Move debug loc info along when the spiller creates new instructions. 
llvm-svn: 64342
 2009-02-12 00:02:55 +00:00
Evan Cheng
64dfcacd5f Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty 
suprise to some callers, e.g. register coalescer. For now, add an parameter
that tells AnalyzeBranch whether it's safe to modify the mbb. A better
solution is out there, but I don't have time to deal with it right now.

llvm-svn: 64124
 2009-02-09 07:14:22 +00:00
Evan Cheng
066757eea1 Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo. 
llvm-svn: 63938
 2009-02-06 17:43:24 +00:00
Bill Wendling
e3c78361d3 Create DebugLoc information in FastISel. Several temporary methods were 
created. Specifically, those BuildMIs which use
"DebugLoc::getUnknownLoc()". I'll remove them soon.

llvm-svn: 63584
 2009-02-03 00:55:04 +00:00
Evan Cheng
c544cb0eca Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well. 
llvm-svn: 62600
 2009-01-20 19:12:24 +00:00
Evan Cheng
d5021730c8 Preliminary ARM debug support based on patch by Mikael of FlexyCore. 
llvm-svn: 60851
 2008-12-10 21:54:21 +00:00
Dan Gohman
3f86b51333 Split foldMemoryOperand into public non-virtual and protected virtual 
parts, and add target-independent code to add/preserve
MachineMemOperands.

llvm-svn: 60488
 2008-12-03 18:43:12 +00:00
Dan Gohman
0b2732598c Add more const qualifiers. This fixes build breakage from r59540. 
llvm-svn: 59542
 2008-11-18 19:49:32 +00:00
Evan Cheng
3620e685b5 Minor code restructuring. No functionality change. 
llvm-svn: 58643
 2008-11-03 21:02:39 +00:00
Dan Gohman
33332bce17 Const-ify several TargetInstrInfo methods. 
llvm-svn: 57622
 2008-10-16 01:49:15 +00:00
Dan Gohman
0d1e9a8e04 Switch the MachineOperand accessors back to the short names like 
isReg, etc., from isRegister, etc.

llvm-svn: 57006
 2008-10-03 15:45:36 +00:00
Owen Anderson
27fb3dcbc7 Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested 
was inserted or not.  This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.

llvm-svn: 55375
 2008-08-26 18:03:31 +00:00
Owen Anderson
4f6bf04616 Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API. 
llvm-svn: 54802
 2008-08-14 22:49:33 +00:00
Dan Gohman
3b46030375 Pool-allocation for MachineInstrs, MachineBasicBlocks, and 
MachineMemOperands. The pools are owned by MachineFunctions.

This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.

llvm-svn: 53212
 2008-07-07 23:14:23 +00:00
Evan Cheng
7d98a48f15 - Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. 
- Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list.

llvm-svn: 53097
 2008-07-03 09:09:37 +00:00
Owen Anderson
30cc028e4a Make LiveVariables even more optional, by making it optional in the call to TargetInstrInfo::convertToThreeAddressInstruction 
Also, if LV isn't around, then TwoAddr doesn't need to be updating flags, since they won't have been set in the first place.

llvm-svn: 53058
 2008-07-02 23:41:07 +00:00
Dan Gohman
fb19f9402b Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminating 
the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.

Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.

This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.

llvm-svn: 52943
 2008-07-01 00:05:16 +00:00
Nicolas Geoffray
ae84bbdbed Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented 
llvm-svn: 49809
 2008-04-16 20:10:13 +00:00
Evan Cheng
ed6e34fe41 Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo. 
llvm-svn: 48995
 2008-03-31 20:40:39 +00:00
Chris Lattner
0f760dfe09 Fix "Control reaches the end of non-void function" warnings, 
patch by David Chisnall.

llvm-svn: 48963
 2008-03-30 18:22:13 +00:00
Evan Cheng
0e7b00d79f Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF. 
llvm-svn: 48380
 2008-03-15 00:03:38 +00:00
Evan Cheng
6325446666 Refactor code. Remove duplicated functions that basically do the same thing as 
findRegisterUseOperandIdx, findRegisterDefOperandIndx. Fix some naming inconsistencies.

llvm-svn: 47927
 2008-03-05 00:59:57 +00:00
Dan Gohman
3a4be0fdef Rename MRegisterInfo to TargetRegisterInfo. 
llvm-svn: 46930
 2008-02-10 18:45:23 +00:00
Evan Cheng
3b3286d4bc It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned. 
llvm-svn: 46893
 2008-02-08 21:20:40 +00:00
Owen Anderson
1ba66e0cec Remove DefInst from LiveVariables::VarInfo. Use the facilities on MachineRegisterInfo instead. 
llvm-svn: 46016
 2008-01-15 22:02:46 +00:00
Chris Lattner
596875118c rename MachineInstr::setInstrDescriptor -> setDesc 
llvm-svn: 45871
 2008-01-11 18:10:50 +00:00
Evan Cheng
7250120177 Only mark instructions that load a single value without extension as isSimpleLoad = 1. 
llvm-svn: 45727
 2008-01-07 23:56:57 +00:00
Chris Lattner
03ad885039 rename TargetInstrDescriptor -> TargetInstrDesc. 
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.

llvm-svn: 45695
 2008-01-07 07:27:27 +00:00
Chris Lattner
e99a6caee4 Rename all the M_* flags to be namespace qualified enums, and switch 
all clients over to using predicates instead of these flags directly.
These are now private values which are only to be used to statically
initialize the tables.

llvm-svn: 45692
 2008-01-07 06:42:05 +00:00
Chris Lattner
b0d06b4381 Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor 
llvm-svn: 45680
 2008-01-07 03:13:06 +00:00