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397 Commits

Author SHA1 Message Date
Chris Lattner
86e1c9484f avoid needless throw/catch/rethrow, stringref'ize some simple stuff. 
llvm-svn: 117892
 2010-11-01 03:19:09 +00:00
Chris Lattner
a397716081 eliminate the old InstFormatName which is always "AsmString", 
simplify CodeGenInstruction. No functionality change.

llvm-svn: 117891
 2010-11-01 02:15:23 +00:00
Chris Lattner
517dc95d47 all predicates on an MnemonicAlias must be AssemblerPredicates. 
llvm-svn: 117890
 2010-11-01 02:09:21 +00:00
Chris Lattner
f7a01e9f46 change the singleton register handling code to be based on Record*'s 
instead of strings, simplifying it.

llvm-svn: 117889
 2010-11-01 01:47:07 +00:00
Chris Lattner
b80ab36179 Give AsmMatcherInfo a CodeGenTarget, which simplifies a bunch of 
argument passing.  Consolidate all SingletonRegister detection
and handling into a new 
InstructionInfo::getSingletonRegisterForToken method instead of
having it scattered about.  No change in generated .inc files.

llvm-svn: 117888
 2010-11-01 01:37:30 +00:00
Chris Lattner
25d9c7fa2e move FlattenVariants out of AsmMatcherEmitter into a shared 
CodeGenInstruction::FlattenAsmStringVariants method.  Use it
to simplify the code in AsmWriterInst, which now no longer 
needs to worry about variants.

llvm-svn: 117886
 2010-11-01 01:07:14 +00:00
Chris Lattner
40dd3f0939 add a FIXME, $lane in ARM is an issue that needs to be resolved before 
this can start rejecting instructions.

llvm-svn: 117885
 2010-11-01 00:51:32 +00:00
Chris Lattner
941c19b7ba reject instructions that contain a \n in their asmstring. Mark 
various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.

llvm-svn: 117884
 2010-11-01 00:46:16 +00:00
Chris Lattner
7ff334687d fix the !eq operator in tblgen to return a bit instead of an int. 
Use this to make the X86 and ARM targets set isCodeGenOnly=1 
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.

llvm-svn: 117862
 2010-10-31 19:22:57 +00:00
Chris Lattner
9492c17baf two changes: make the asmmatcher generator ignore ARM pseudos properly, 
and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.

llvm-svn: 117861
 2010-10-31 19:15:18 +00:00
Chris Lattner
33fc3e095b reapply r117858 with apparent editor malfunction fixed (somehow I 
got a dulicated line).

llvm-svn: 117860
 2010-10-31 19:10:56 +00:00
Chris Lattner
e59eef3dd1 revert r117858 while I check out a failure I missed. 
llvm-svn: 117859
 2010-10-31 19:05:32 +00:00
Chris Lattner
9293008e90 the asm matcher can't handle operands with modifiers (like ${foo:bar}). 
Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the 
instruction 'isCodeGenOnly'.

Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are 
doing this.

llvm-svn: 117858
 2010-10-31 18:48:12 +00:00
Chris Lattner
43690071cf have GetAliasRequiredFeatures get its features from 
AsmMatcherInfo so we don't have two places that know the
feature -> enum mapping.  No functionality change.

llvm-svn: 117845
 2010-10-30 20:15:02 +00:00
Chris Lattner
a0e871901b simplify code that creates SubtargetFeatureInfo, ensuring that features 
that are only used by MnemonicAliases will be found.

llvm-svn: 117844
 2010-10-30 20:07:57 +00:00
Chris Lattner
f9ec2fb34a fix typos and some serious bugs in feature handling (but not for 
cases that are currently exercised).  Thanks to Frits van Bommel for
the great review!

llvm-svn: 117840
 2010-10-30 19:47:49 +00:00
Chris Lattner
aac142cc06 Resolve a terrible hack in tblgen: instead of hardcoding 
"In32BitMode" and "In64BitMode" into tblgen, allow any
predicate that inherits from AssemblerPredicate.

llvm-svn: 117831
 2010-10-30 19:38:20 +00:00
Chris Lattner
2cb092dc55 Implement (and document!) support for MnemonicAlias's to have Requires 
directives, allowing things like this:

def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;

Move the rest of the X86 MnemonicAliases over to the .td file.

llvm-svn: 117830
 2010-10-30 19:23:13 +00:00
Chris Lattner
ec56397eb4 fix build problem 
llvm-svn: 117828
 2010-10-30 18:57:07 +00:00
Chris Lattner
cf9b6e3107 diagnose targets that define two alises with the same 'from' mnemonic 
with a useful error message instead of having tblgen explode with an 
assert.

llvm-svn: 117827
 2010-10-30 18:56:12 +00:00
Chris Lattner
477fba4f54 emit the mnemonic aliases in their own helper function instead of 
inline into MatchInstructionImpl.

llvm-svn: 117826
 2010-10-30 18:48:18 +00:00
Chris Lattner
ba7b4fea97 implement (and document!) the first kind of MC assembler alias, which 
just remaps one mnemonic to another.  Convert a few of the X86 aliases
from .cpp to .td code.

llvm-svn: 117815
 2010-10-30 17:36:36 +00:00
Jim Grosbach
0eccfc2693 trailing whitespace 
llvm-svn: 117724
 2010-10-29 22:13:48 +00:00
Chris Lattner
1be0697ab9 fix the asmmatcher generator to handle targets with no RegisterPrefix 
(like ARM) correctly.  With this change, we can now match "bx lr"
because we recognize lr as a register.

llvm-svn: 117606
 2010-10-28 21:28:42 +00:00
Jim Grosbach
b75d0ca38e A few 80 column cleanups 
llvm-svn: 116069
 2010-10-08 18:13:57 +00:00
Chris Lattner
6282336772 attempt to appease msvc 
llvm-svn: 113198
 2010-09-07 06:10:48 +00:00
Gabor Greif
7f3ce25e6e fix comment typos 
llvm-svn: 113197
 2010-09-07 06:06:06 +00:00
Chris Lattner
abfe4223c2 generalize my previous operand loc info hack. If the same operand 
is busted for all variants, report it as the location.  This allows
us to get the operand right for bugs like:

t.s:3:12: error: invalid operand for instruction
	outb %al, %gs
	          ^

Even though there are reg/imm and reg/reg forms of this instruction.

llvm-svn: 113183
 2010-09-06 23:37:39 +00:00
Chris Lattner
339cc7bfef in the case where an instruction only has one implementation 
of a mneumonic, report operand errors with better location
info.  For example, we now report:

t.s:6:14: error: invalid operand for instruction
        cwtl $1
             ^

but we fail for common cases like:

t.s:11:4: error: invalid operand for instruction
   addl $1, $1
   ^

because we don't know if this is supposed to be the reg/imm or imm/reg
form.

llvm-svn: 113178
 2010-09-06 22:11:18 +00:00
Chris Lattner
628fbecf4f Now that we know if we had a total fail on the instruction mnemonic, 
give a more detailed error.  Before:

t.s:11:4: error: unrecognized instruction
   addl $1, $1
   ^
t.s:12:4: error: unrecognized instruction
   f2efqefa $1
   ^

After:

t.s:11:4: error: invalid operand for instruction
   addl $1, $1
   ^
t.s:12:4: error: invalid instruction mnemonic 'f2efqefa'
   f2efqefa $1
   ^

This fixes rdar://8017912 - llvm-mc says "unrecognized instruction" when it means "invalid operands"

llvm-svn: 113176
 2010-09-06 21:54:15 +00:00
Chris Lattner
c0658cbd16 simplify DEBUG_WITH_TYPE usage 
llvm-svn: 113174
 2010-09-06 21:28:52 +00:00
Chris Lattner
c4521d1b5f this if can now be an assert. 
llvm-svn: 113173
 2010-09-06 21:25:43 +00:00
Chris Lattner
9026ac0edd ; 
llvm-svn: 113172
 2010-09-06 21:23:43 +00:00
Chris Lattner
8130197937 now that the opcode is trivially exposed, start matching instructions 
by doing a binary search over the mnemonic instead of doing a linear
search through all possible instructions.  This implements rdar://7785064

llvm-svn: 113171
 2010-09-06 21:22:45 +00:00
Chris Lattner
6b6f3dd994 emit the match table at global scope instead of within the 
MatchInstructionImpl. This makes it easier to read/understand
MatchInstructionImpl.

llvm-svn: 113170
 2010-09-06 21:08:38 +00:00
Chris Lattner
82d88ced92 special case the mnemonic operand of the instruction in the 
generated matcher, emiting it as a column in the MatchEntry
table instead of forcing it to go through classification and
everything else.  Making it be classified caused tblgen to
produce a ton of one-off classes for each mneumonic.  This
should reduce the size of the generated matcher significantly
while paving the way for future improvements.

llvm-svn: 113169
 2010-09-06 21:01:37 +00:00
Chris Lattner
fdb7decfaf The "ambiguous instructions" check only produces anything with -debug, 
so only do the N^2 loop with debug mode.

llvm-svn: 113168
 2010-09-06 20:21:47 +00:00
Chris Lattner
b4be28f33d have tblgen detect when an instruction would have matched, but 
failed because a subtarget feature was not enabled.  Use this to
remove a bunch of hacks from the X86AsmParser for rejecting things
like popfl in 64-bit mode.  Previously these hacks weren't needed,
but were important to get a message better than "invalid instruction"
when used in the wrong mode.

This also fixes bugs where pushal would not be rejected correctly in
32-bit mode (just pusha).

llvm-svn: 113166
 2010-09-06 20:08:02 +00:00
Chris Lattner
a22a368e7c change MatchInstructionImpl to return an enum instead of bool. 
llvm-svn: 113165
 2010-09-06 19:22:17 +00:00
Chris Lattner
3e4582ada5 have AsmMatcherEmitter.cpp produce the hunk of code that gets included 
into the middle of the class, and rework how the different sections of
the generated file are conditionally included for simplicity.

llvm-svn: 113163
 2010-09-06 19:11:01 +00:00
Chris Lattner
ca5a3554b5 factor the snazzy string matcher code that Daniel hates 
out of AsmMatcherEmitter.cpp into its own class.

llvm-svn: 113137
 2010-09-06 02:01:51 +00:00
Daniel Dunbar
167b9d7f30 tblgen/AsmMatcher: Always emit the match function as 'MatchInstructionImpl', 
target specific parsers can adapt the TargetAsmParser to this.

llvm-svn: 110888
 2010-08-12 00:55:32 +00:00
Daniel Dunbar
69f024b855 tblgen/AsmMatcher: Treat '.' in assembly strings as a token separator. 
llvm-svn: 110789
 2010-08-11 06:36:59 +00:00
Daniel Dunbar
1326056108 tblgen/AsmMatcher: Downgrade instructions with tied operands to a debug-only warning, for now. 
llvm-svn: 110779
 2010-08-11 04:46:08 +00:00
Daniel Dunbar
eefe8616be TblGen/AsmMatcher: Add support for honoring instruction Requires<[]> attributes as part of the matcher. 
- Currently includes a hack to limit ourselves to "In32BitMode" and "In64BitMode", because we don't have the other infrastructure to properly deal with setting SSE, etc. features on X86.

llvm-svn: 108677
 2010-07-19 05:44:09 +00:00
Duncan Sands
41b4a6b36a Convert some tab stops into spaces. 
llvm-svn: 108130
 2010-07-12 08:16:59 +00:00
Daniel Dunbar
97ac3afac2 AsmMatcher: Ensure classes are totally ordered, so we can std::sort them reliably. 
llvm-svn: 104806
 2010-05-27 05:31:32 +00:00
Daniel Dunbar
346782c12c tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses instead of just one. 
llvm-svn: 104452
 2010-05-22 21:02:29 +00:00
Daniel Dunbar
9989417f33 MC/Matcher: Add support for over-riding the default MatchInstruction function 
name (for example, to allow targets to interpose the actual MatchInstruction
function).

llvm-svn: 102987
 2010-05-04 00:33:13 +00:00
Chris Lattner
918be520dc change Target.getInstructionsByEnumValue to return a reference 
to a vector that CGT stores instead of synthesizing it on every 
call.

llvm-svn: 98910
 2010-03-19 00:34:35 +00:00