4362 Commits

Author SHA1 Message Date
Nikita Popov
6642cc60a2 [SCEV] Add tests for ule/sle exit counts (NFC) 2024-05-15 11:10:46 +09:00
Florian Hahn
179efe5abc
[LAA] Delay applying loop guards until after isSafeDependenceDistance.
Applying the loop guards to the distance may prevent
isSafeDependenceDistance from determining NoDep, unless loop guards are
also applied to the backedge-taken-count.

Instead of applying the guards to both Dist and the
backedge-taken-count, just apply them after handling
isSafeDependenceDistance and constant distances; there is no benefit to
applying the guards before then.

This fixes a regression flagged by @bjope due to
ecae3ed958481cba7d60868cf3504292f7f4fdf5.
2024-05-14 19:47:24 +01:00
Florian Hahn
86f655cb4e
[LAA] Add tests showing unnecessary RT check due to applying loop guards
Test courtesy to @bjope showing a regression due to
ecae3ed958481cba7d60868cf3504292f7f4fdf5.
2024-05-14 18:27:37 +01:00
Min-Yih Hsu
4c68de5a00
[RISCV][CostModel] Add cost model for experimental.cttz.elts (#91778)
The cost of `experimental.cttz.elts` in RISC-V equals to the cost of
vfirst when the zero_is_poison argument is true. Otherwise, we add
additional costs of cmp + select to convert the -1 result from vfirst to
EVL.
2024-05-14 09:18:08 -07:00
Hari Limaye
d9be51ce68
[AArch64] Improve code generation for experimental.cttz.elts (#91505)
This patch extends support for lowering the experimental.cttz.elts
intrinsic to BRKB + CNTP instruction sequences, using this lowering for
all legal predicate types. An unused parameter is also removed from some
of the related regression tests.
2024-05-14 09:49:53 +01:00
Nikita Popov
05a97a1a51 [MustExec] Drop duplicate RUN line (NFC) 2024-05-14 12:22:14 +09:00
Shih-Po Hung
22213d5883 Recommit [RISCV][TTI] Support fdiv/udiv/sdiv/srem/urem in getArithmeticInstrCost (#89170)
Insert a break to fix the implicit-fallthrough caught by sanitizer.

Original commit message:

This patch made following changes:
1. Support ISD FDIV/UDIV/SDIV/UREM/SREM
2. Classify instructions which cost the same
2024-05-12 20:10:51 -07:00
ShihPo Hung
d67c3a4b1f Revert "[RISCV][TTI] Support fdiv/udiv/sdiv/srem/urem in getArithmeticInstrCost (#89170)"
This reverts commit ed16e7aac44f2024b45d8c6c9dc2817d77d0ea97.
2024-05-12 19:57:40 -07:00
Shih-Po Hung
ed16e7aac4
[RISCV][TTI] Support fdiv/udiv/sdiv/srem/urem in getArithmeticInstrCost (#89170)
This patch made following changes:
1. Support ISD FDIV/UDIV/SDIV/UREM/SREM
2. Classify instructions which cost the same
2024-05-13 09:47:57 +08:00
Simon Pilgrim
23fe1fc6b7 [TTI][X86] getGSScalarCost - don't bother with adding cost of ICMP for each i1 mask element
These can nearly always be folded into the existing cost of the branch, and brings the throughput costs of the scalarised gather/scatter code much closer to the llvm-mca/uica estimates
2024-05-11 13:37:48 +01:00
Simon Pilgrim
079fdef7d2 [TTI] getCommonMaskedMemoryOpCost - use the target getMemoryOpCost/getCFInstrCost implementations.
We were using the default implementations instead of the CRTP versions.
2024-05-11 12:50:26 +01:00
Florian Hahn
f52ca63278
[LAA] Drop x86_64 target triple to fix test on builds with X86.
Follow-up o fix test after 28767afd53353d9333b0adf6f0fafa1592092532.
2024-05-10 12:27:24 +01:00
Florian Hahn
28767afd53
[LAA] Support backward dependences with non-constant distance. (#91525)
Following up to 933f49248, also update the code reasoning about
backwards dependences to support non-constant distances.

Update the code to use the signed minimum distance instead of a constant
distance

This means e checked the lower bound of the dependence distance and the
distance may be larger at runtime (and safe for vectorization). Whether
to classify it as Unknown or Backwards depends on the vector width and
LAA was updated to take TTI to get the maximum vector register width.

If the minimum dependence distance is larger than the max vector width,
we consider it as backwards-vectorizable. Otherwise we classify them as
Unknown, so we re-try with runtime checks.

PR: https://github.com/llvm/llvm-project/pull/91525
2024-05-10 11:47:13 +01:00
Florian Hahn
ecae3ed958
[LAA] Apply loop guards to dependence distance.
After supporting non-constant dependence distances in 933f49248bf,
applying information from loop guards can help further disambiguate
dependencies.
2024-05-09 18:12:55 +01:00
David Sherwood
b52fa9461a
[Analysis] Add cost model for experimental.cttz.elts intrinsic (#90720)
In PR #88385 I've added support for auto-vectorisation of some early
exit loops, which requires using the experimental.cttz.elts to calculate
final indices in the early exit block. We need a more accurate cost
model for this intrinsic to better reflect the cost of work required in
the early exit block. I've tried to accurately represent the expansion
code for the intrinsic when the target does not have efficient lowering
for it. It's quite tricky to model because you need to first figure out
what types will actually be used in the expansion. The type used can
have a significant effect on the cost if you end up using illegal vector
types.

Tests added here:

  Analysis/CostModel/AArch64/cttz_elts.ll
  Analysis/CostModel/RISCV/cttz_elts.ll
2024-05-09 09:40:33 +01:00
Florian Hahn
1464aee376
[LAA] Add tests with non-constant backward deps with known min value.
Add a set of tests with non-constant backward dependences, where the
minimum value is known (via the start value of the outer AddRec).
2024-05-08 20:16:46 +01:00
Simon Pilgrim
a55127281b [CostModel][X86] getGSVectorCost - add cost kind support
Don't just assume gather/scatter non-throughput costs are 1 - latency and sizelatency (#uops) costs will be high, and codesize (#instructions) needs to account splitting.
2024-05-08 16:24:39 +01:00
Florian Hahn
50b45b2422
[LAA] Add tests with forward dependences known via assumes. 2024-05-08 15:45:38 +01:00
Florian Hahn
40b322baef
[SCEV] Add tests for missed NSW preservation during loop guard handling.
Add test coverage for missed simplification.
2024-05-08 14:46:28 +01:00
Chris Copeland
651bdb96b1
[ARM] Armv8-R does not require fp64 or neon. (#88287)
This was [addressed for AArch64
here](https://github.com/llvm/llvm-project/pull/79004), but the same
applies to ARM.

Move the enablement of neon+fp64 to `-mcpu=cortex-r52`, which optionally
supports these features.
2024-05-07 11:48:30 +01:00
Simon Pilgrim
abd314938d
[X86] Use GFNI for vXi8 shifts/rotates (#89115)
As detailed here: https://github.com/InstLatx64/InstLatX64_Demo/blob/master/GFNI_Demo.h

We can use the gf2p8affine instruction to lower byte shifts/rotates as well as the existing bitreverse case.

Based off the original patch here: https://reviews.llvm.org/D137026
2024-05-07 10:28:55 +01:00
Monad
fd0ffb7438
[ValueTracking] Recognize LShr(UINT_MAX, Y) + 1 as a power-of-two (#91171)
There is a missed optimization in
``` llvm
define i8 @known_power_of_two_rust_next_power_of_two(i8 %x, i8 %y) {
  %2 = add i8 %x, -1
  %3 = tail call i8 @llvm.ctlz.i8(i8 %2, i1 true)
  %4 = lshr i8 -1, %3
  %5 = add i8 %4, 1
  %6 = icmp ugt i8 %x, 1
  %p = select i1 %6, i8 %5, i8 1

  %r = urem i8 %y, %p
  ret i8 %r
}
```
which is extracted from the Rust code
``` rust
fn func(x: usize, y: usize) -> usize {
    let z = x.next_power_of_two();
    y % z
}
```
Here `%p` (a.k.a `z`) is semantically a power-of-two, so `y urem p` can
be optimized to `y & (p - 1)`. (Alive2 proof:
https://alive2.llvm.org/ce/z/H3zooY)

---

It could be generalized to recognizing `LShr(UINT_MAX, Y) + 1` as a
power-of-two, which is what this PR does.
Alive2 proof: https://alive2.llvm.org/ce/z/zUPTbc
2024-05-07 10:28:36 +09:00
Florian Hahn
5f73d29cb7
[LAA] Add tests showing extra unnecessary runtime checks.
Pre-commit tests for an upcoming patch.
2024-05-06 13:14:33 +01:00
Florian Hahn
148b721772
[LAA] Update check line in test to fully match message. 2024-05-06 13:04:36 +01:00
Sameer Sahasrabuddhe
8a65ee8b2a
[AMDGPU] don't mark control-flow intrinsics as convergent (#90026)
This is really a workaround to allow control flow lowering in the
presence of convergence control tokens. Control-flow intrinsics in LLVM
IR are convergent because they indirectly represent the wave CFG, i.e.,
sets of threads that are "converged" or "execute in lock-step". But they
exist during a small window in the lowering process, inserted after the
structurizer and then translated to equivalent MIR pseudos. So rather
than create convergence tokens for these builtins, we simply mark them
as not convergent.

The corresponding MIR pseudos are marked as having side effects, which
is sufficient to prevent optimizations without having to mark them as
convergent.
2024-05-06 14:07:11 +05:30
Fangrui Song
b9ae06ba15 [test] Convert text files from CRLF to LF
Skip *.pdb, *.rc, *crlf*, and FileCheck/dos-style-eol.txt
2024-05-03 10:09:52 -07:00
Simon Pilgrim
8a0073ad46
[CostModel][X86] Treat lrint/llrint as fptosi calls (#90883)
X86 can use the CVTP2SI instructions to lower lrint/llrint calls, which have the same costs as the CVTTP2SI (fptosi) instructions

Followup to #90065
2024-05-03 18:06:50 +01:00
Simon Pilgrim
fc7e74e879 [CostModel][X86] getCastInstrCost - improve CostKind adjustment when splitting src/dst types
Noticed in #90883 review - for non-Throughput costs, we weren't applying the split count to '0 or 1' cost value.

This still doesn't work well as many of the type legalizations are hidden so we don't have the split count, really we need to move a CostKindCosts based costs table, but that's going to be a lot of work :/
2024-05-03 12:17:18 +01:00
Simon Pilgrim
49bac13acd [CostModel][X86] Add test coverage for rint/lrint/llrint fp calls 2024-05-02 18:51:35 +01:00
Nikita Popov
74aa1abfae
[InstCombine] Canonicalize scalable GEPs to use llvm.vscale intrinsic (#90569)
Canonicalize getelementptr instructions for scalable vector types into
ptradd representation with an explicit llvm.vscale call. This
representation has better support in BasicAA, which can reason about
llvm.vscale, but not plain scalable GEPs.
2024-05-01 14:53:43 +09:00
Florian Hahn
82219e547b
[LAA] Pass maximum stride to isSafeDependenceDistance. (#90036)
As discussed in https://github.com/llvm/llvm-project/pull/88039, support
different strides with isSafeDependenceDistance by passing the maximum
of both strides.

isSafeDependenceDistance tries to prove that
    |Dist| > BackedgeTakenCount * Step
holds. Chosing the maximum stride computes the maximum range accesed by
the loop for all strides.

PR: https://github.com/llvm/llvm-project/pull/90036
2024-04-30 12:59:08 +01:00
Maciej Gabka
bfc0317153
Move several vector intrinsics out of experimental namespace (#88748)
This patch is moving out following intrinsics:
* vector.interleave2/deinterleave2
* vector.reverse
* vector.splice

from the experimental namespace.

All these intrinsics exist in LLVM for more than a year now, and are
widely used, so should not be considered as experimental.
2024-04-29 10:16:45 +01:00
Shih-Po Hung
6cd6bde309
[RISCV] Remove -riscv-v-fixed-length-vector-lmul-max from arith tests (#89886)
This patch splits off from #89170 to clean up the tests.
2024-04-29 13:48:08 +08:00
Florian Hahn
933f49248b
[LAA] Support different strides & non constant dep distances using SCEV. (#88039)
Extend LoopAccessAnalysis to support different strides and as a
consequence non-constant distances between dependences using SCEV to
reason about the direction of the dependence.

In multiple places, logic to rule out dependences using the stride has
been updated to only be used if StrideA == StrideB, i.e. there's a
common stride.

We now also may bail out at multiple places where we may have to set
FoundNonConstantDistanceDependence. This is done when we need to bail
out and the distance is not constant to preserve original behavior.

Fixes https://github.com/llvm/llvm-project/issues/87336

PR: https://github.com/llvm/llvm-project/pull/88039
2024-04-25 21:38:07 +01:00
Florian Hahn
d5f2753067
[LAA] Tests with different strides where BTC can rule out dependence.
Tests to add support for different strides with isSafeDependenceDistance
as follow-up to https://github.com/llvm/llvm-project/pull/88039.
2024-04-25 10:44:36 +01:00
David Sherwood
96b2e35a58
[CostModel][AArch64] Improve fixed-width vector costs for get.active.lane.mask (#89068)
When SVE is available we can lower calls to get.active.lane.mask using
the SVE whilelo instruction, however in practice since vXi1 types are
not legal for NEON we often end up expanding the predicate into a vector
of integers, e.g. v4i1 -> v4i32. This usually happens when we have to
keep the predicate live out of the block, for example when the predicate
is the incoming value to a PHI node in a tail-folded vector loop.
Currently in such cases the intrinsic call has a cost of 1, which is far
too low when considering the extra instructions required to expand the
predicate. This patch fixes that by basing the cost on the number of
lane moves required for expansion. This is required for a follow-on
patch that adds the cost of the intrinsic call to the vectorisation cost
model, so that we can teach the vectoriser to make better choices.
2024-04-24 14:31:06 +01:00
Noah Goldstein
b933c8447b [ValueTracking] Add support for trunc nuw/nsw in isKnowNonZero
With `nsw`/`nuw`, the `trunc` is non-zero if its operand is non-zero.

Proofs: https://alive2.llvm.org/ce/z/iujmk6

Closes #89643
2024-04-24 02:53:11 -05:00
Noah Goldstein
b3ca9c30de [ValueTracking] Add tests for isKnowNonZero of trunc nuw/nsw; NFC 2024-04-24 02:53:11 -05:00
Simon Pilgrim
f89f670d92 [CostModel][X86] Broadcast shuffles can be free if they are from a one-use load
AVX1+ can handle 32/64-bit broadcast loads, AVX2+ can handle all broadcast loads (we should be able to improve isLegalBroadcastLoad to handle more of this type matching).
2024-04-23 11:11:15 +01:00
Simon Pilgrim
a9e87304a3 [CostModel][X86] Add costs test coverage for broadcast loads
Broadcast shuffles can be free is fed from a one-use load
2024-04-23 11:11:14 +01:00
Florian Hahn
5138ccd0e4
[LAA] Add etra tests with strides with different signs.
Extra tests with strides with different signs for
https://github.com/llvm/llvm-project/pull/88039.
2024-04-22 15:50:59 +01:00
David Green
18bb175428 [AArch64] Add costs for LD3/LD4 shuffles.
Similar to #87934, this adds costs to the shuffles in a canonical LD3/LD4
pattern, which are represented in LLVM as deinterleaving-shuffle(load). This
likely has less effect at the moment than the ST3/ST4 costs as instcombine will
perform certain transforms without considering the cost.
2024-04-21 13:53:22 +01:00
Michael Liao
5b4ed0dc9f [test] Fix test. NFC
- Add the missing token in @llvm.coro.end
2024-04-19 14:23:09 -04:00
Matthias Braun
6bbccd2516
GlobalsModRef, ValueTracking: Look through threadlocal.address intrinsic (#88418)
This improves handling of `threadlocal.address` intrinsic in analyses:

The thread-id cannot change within a function with the exception of
suspend points of pre-split coroutines. This changes
`llvm::getUnderlyingObject` to look through `threadlocal.address` in
these cases.

`GlobalsAAResult::AnalyzeUsesOfPointer` checks whether an address can be
traced to simple loads/stores or escapes to other places. Starting the
analysis from a thread-local `GlobalValue` the `threadlocal.address`
intrinsic is safe to skip here.

This improves issue #87437
2024-04-19 10:01:42 -07:00
Shih-Po Hung
097b68ff06
[RISCV][TTI] Refine the cost of FCmp (#88833)
This patch introduces following changes
- Support all fp predicates
- Use the Val type to estimate the latency/throughput cost
- Assign a cost of 1 for mask operations as LMULCost for mask types
cannot be correctly estimated.
2024-04-18 09:44:31 +08:00
David Green
4572a2db2c [AArch64] Add some test cases for LD2/LD3/LD4 shuffles. NFC 2024-04-17 19:44:17 +01:00
Simon Pilgrim
c02ed29ec1 [CostModel][X86] Recognise vector rotation by uniform constant patterns
Adds suitable costs for AVX512 targets (we still rely on default expansion for AVX2 and earlier)
2024-04-17 19:08:36 +01:00
Simon Pilgrim
825536039d [CostModel][X86] Add basic GFNI target test coverage for shift/rotate costs 2024-04-17 18:35:17 +01:00
Simon Pilgrim
e49043512d [CostModel][X86] Update BITREVERSE costs for GFNI targets
Inspired by the recent patches by @shamithoke - we have real scheduler model numbers for GFNI instructions now, allowing us to calculate an upper bounds costs table instead of performing it analytically.
2024-04-17 15:46:38 +01:00
Shih-Po Hung
f3a8112d98
[RISCV][TTI] Scale the cost of ICmp with LMUL (#88235)
Use the Val type to estimate the instruction cost for ICmp.
2024-04-16 09:37:32 +08:00