107486 Commits

Author SHA1 Message Date
David Green
8a701024f3 [ARM] Lower i1 concat via MVETRUNC
The MVETRUNC operation can perform the same truncate of two vectors, without
requiring lane inserts/extracts from every vector lane. This moves the concat
i1 lowering to use it for v8i1 and v16i1 result types, trading a bit of extra
stack space for less instructions.
2023-10-18 19:40:11 +01:00
Stanislav Mekhanoshin
84f398af74
[AMDGPU] Add missing test checks. NFC. (#69484) 2023-10-18 11:26:39 -07:00
Luke Lau
3927b9ab11 [VectorCombine] Add tests for unspeculatable VP binops. NFC
The current test cases to guard against speculative execution can actually be
safely speculated because the denominator is known to be not 0 or -1, and
isSafeToSpeculativelyExecuteWithOpcode will account for this. This adds some
more test cases and rejigs some existing ones to use an unknown variable
instead.
2023-10-18 14:23:02 -04:00
Oskar Wirga
c9b7d21dc5
[CFI/MergeFunctions] Modify MergeFunctions to propagate type information (#68628)
When MergeFuncs creates a thunk, it does not modify the function in
place, but creates a new one altogether. If type metadata is not
properly forwarded to this new function, LowerTypeTests will be unable
to put this thunk into the dispatch table.

The fix here is to just forward the type metadata to the newly created
functions.
2023-10-18 11:22:35 -07:00
Ilya Leoshkevich
8e810dc7d9
[SystemZ] Support builtin_{frame,return}_address() with non-zero argument (#69405)
When the code is built with -mbackchain, it is possible to retrieve the
caller's frame and return addresses. GCC already can do this, add this
support to Clang as well. Use RISCVTargetLowering and GCC's
s390_return_addr_rtx() as inspiration. Add tests based on what GCC is
emitting.
2023-10-18 19:05:31 +02:00
Stanislav Mekhanoshin
47ed921985
[AMDGPU] Add legality check when folding short 64-bit literals (#69391)
We can only fold it if it can fit into 32-bit. I believe it did not
trigger yet because we do not select 64-bit literals generally.
2023-10-18 09:22:23 -07:00
Alex Langford
814a79aea6
[DebugInfo] Separate error generation from reporting in DWARFHeaderUnit::extract (#68242)
Instead of reporting the error directly through the DWARFContext passed
in as an argument, it would be more flexible to have extract return the
error and allow the caller to react appropriately.

This will be useful for using llvm's DWARFHeaderUnit from lldb which may
report header extraction errors through a different mechanism.
2023-10-18 09:06:39 -07:00
Valery Dmitriev
c80b503496
[SLP] Improve gather tree nodes matching when users are PHIs. (#69392) 2023-10-18 09:05:11 -07:00
Stephen Tozer
df3478e480
[LLVM] Add new attribute optdebug to optimize for debugging (#66632)
This patch adds a new fn attribute, `optdebug`, that specifies that
optimizations should make decisions that prioritize debug info quality,
potentially at the cost of runtime performance.

This patch does not add any functional changes triggered by this
attribute, only the attribute itself. A subsequent patch will use this
flag to disable the post-RA scheduler.
2023-10-18 16:32:06 +01:00
Florian Hahn
e7432bc343
[InstCombine] Add aligned_alloc with pointer icmp as only use. 2023-10-18 16:09:47 +01:00
Sirish Pande
28e4f97320
[AMDGPU] Save/Restore SCC bit across waterfall loop. (#68363)
Waterfall loop is overwriting SCC bit of status register. Make sure SCC
bit is saved and restored across.
We need to save/restore only in cases where SCC is live across waterfall
loop.

Co-authored-by: Sirish Pande <sirish.pande@amd.com>
2023-10-18 08:43:29 -05:00
David Green
c060757bcc [ARM] Correct v2i1 concat extract types.
For two v2i1 concat into a v4i1, we cannot extract each i64 element as an i32.
This casts to a v4i32 instead and extracts the correct vector lanes.
2023-10-18 13:40:38 +01:00
pvanhout
868abf0961 Revert "[AMDGPU] Remove Code Object V3 (#67118)"
This reverts commit 544d91280c26fd5f7acd70eac4d667863562f4cc.
2023-10-18 12:55:36 +02:00
Jay Foad
104db26004
[AMDGPU] Fix image intrinsic optimizer on loads from different resources (#69355)
The image intrinsic optimizer pass was neglecting to check any arguments
of the load intrinsic after the VAddr arguments. For example multiple
loads from different resources should not have been combined but were,
because the pass was not checking the resource argument.
2023-10-18 11:08:01 +01:00
Paul Walker
675231eb09
[SVE ACLE] Allow default zero initialisation for svcount_t. (#69321)
This matches the behaviour of the other SVE ACLE types.
2023-10-18 10:40:07 +01:00
Amara Emerson
e93bddb287 [AArch64][GlobalISel] Precommit indexed sextload/zextload tests. 2023-10-18 00:23:20 -07:00
Shao-Ce SUN
f48dab5237
Add RV64 constraint to SRLIW (#69416)
Fixes #69408
2023-10-18 15:01:17 +08:00
Noah Goldstein
112e49b381 [DAGCombiner] Transform (icmp eq/ne (and X,C0),(shift X,C1)) to use rotate or to getter constants.
If `C0` is a mask and `C1` shifts out all the masked bits (to
essentially compare two subsets of `X`), we can arbitrarily re-order
shift as `srl` or `shl`.

If `C1` (shift amount) is a power of 2, we can replace the and+shift
with a rotate.

Otherwise, based on target preference we can arbitrarily swap `shl`
and `shl` in/out to get better constants.

On x86 we can use this re-ordering to:
    1) get better `and` constants for `C0` (zero extended moves or
       avoid imm64).
    2) covert `srl` to `shl` if `shl` will be implementable with `lea`
       or `add` (both of which can be preferable).

Proofs: https://alive2.llvm.org/ce/z/qzGM_w

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D152116
2023-10-18 01:16:55 -05:00
Noah Goldstein
0c2d28a448 [X86] Add tests for transform (icmp eq/ne (and X, C0), (shift X, C1)); NFC
Differential Revision: https://reviews.llvm.org/D152115
2023-10-18 01:16:55 -05:00
Pierre van Houtryve
c464fea779
[DAG] Constant fold FMAD (#69324)
This has very little effect on codegen in practice, but is a nice to
have I think.

See #68315
2023-10-18 07:46:24 +02:00
Kai Luo
b42738805a [PowerPC] Auto gen test checks for #69299. NFC. 2023-10-18 02:21:22 +00:00
Nitin John Raj
ae3ba725b7
[RISCV][GlobalISel] Select G_FRAME_INDEX (#68254)
This patch is a bandage to get G_FRAME_INDEX working. We could import
the SelectionDAG patterns for the ComplexPattern FrameAddrRegImm, and
perhaps we will do that in the future. For now we just select it as an
addition with 0.
2023-10-17 17:56:42 -07:00
Valery Dmitriev
3caccb22ab
[NFC][SLP] Test case exposing gather nodes matching deficiency affecting cost. (#69382) 2023-10-17 14:58:10 -07:00
Mircea Trofin
ab91e05e48 [mlgo] Fix tests post 760e7d0 2023-10-17 12:19:54 -07:00
Florian Hahn
fd31112634
[VPlan] Insert Trunc/Exts for reductions directly in VPlan.
Update the code to create Trunc/Ext recipes directly in
adjustRecipesForReductions instead of fixing it up later in
fixReductions.

This explicitly models the required conversions and also makes sure they
are generated at the right place (instead of after the exit condition),
hence the changes in a few tests.
2023-10-17 19:17:40 +01:00
Haowei
dd64c82cbc
[unittest] Allow LLVM unit test to run under a wrapper program. (#66821)
This patch add CMake option "LLVM_GTEST_RUN_UNDER" to LLVM unittest
configuration. When specified, LLVM unittest will be run under the
wrapper program specified by this option. This feature can simplify the
setup to run LLVM unittest on a target platform that is different than
host.
2023-10-17 11:15:46 -07:00
Artem Belevich
b33723710f
[NVPTX] Fixed few more corner cases for v4i8 lowering. (#69263)
Fixes https://github.com/llvm/llvm-project/issues/69124
2023-10-17 11:06:11 -07:00
Stanislav Mekhanoshin
a22a1fe151
[AMDGPU] support 64-bit immediates in SIInstrInfo::FoldImmediate (#69260)
This is a part of https://github.com/llvm/llvm-project/issues/67781.
Until we select more 64-bit move immediates the impact is minimal.
2023-10-17 10:53:22 -07:00
Alexey Bataev
66775f8ccd [SLP]Fix PR69196: Instruction does not dominate all uses
During emission of the postponed gathers, need to insert them before
user instruction to avoid use before definition crash.
2023-10-17 10:43:59 -07:00
David Green
4266815f4d
[AArch64] Convert negative constant aarch64_neon_sshl to VASHR (#68918)
In replacing shifts by splat with constant shifts, we can handle
negative shifts by flipping the sign and using a VASHR or VLSHR.
2023-10-17 18:41:23 +01:00
David Green
658ed58de6 [AArch64] Add additional tests for fptosi/fptoui. NFC 2023-10-17 18:39:37 +01:00
akirchhoff-modular
4480e650b3
[YAMLParser] Improve plain scalar spec compliance (#68946)
The `YAMLParser.h` header file claims support for YAML 1.2 with a few
deviations, but our plain scalar parsing failed to parse some valid YAML
according to the spec. This change puts us more in compliance with the
YAML spec, now letting us parse plain scalars containing additional
special characters in cases where they are not ambiguous.
2023-10-17 11:28:14 -06:00
Guozhi Wei
760e7d00d1 [X86, Peephole] Enable FoldImmediate for X86
Enable FoldImmediate for X86 by implementing X86InstrInfo::FoldImmediate.

Also enhanced peephole by deleting identical instructions after FoldImmediate.

Differential Revision: https://reviews.llvm.org/D151848
2023-10-17 16:22:42 +00:00
Vladislav Dzhidzhoev
abd0d5d262 Reland: [AArch64][GlobalISel] Adopt dup(load) -> LD1R patterns from SelectionDAG
This relands the fb8f59156f0f208f6192ed808fc223eda6c0e7ec and makes
isAArch64FrameOffsetLegal function recognize LD1R instructions.

Original PR: https://github.com/llvm/llvm-project/pull/66914
PR of the fix: https://github.com/llvm/llvm-project/pull/69003
2023-10-17 17:40:05 +02:00
Phoebe Wang
3d6e4160d5
[X86] Enable bfloat type support in inline assembly constraints (#68469)
Similar to FP16 but we don't have native scalar instruction support, so
limit it to vector types only.

Fixes #68149
2023-10-17 22:56:25 +08:00
Weining Lu
b2773d170c [LoongArch] Precommit a test for atomic cmpxchg optmization 2023-10-17 22:29:51 +08:00
XChy
f2898def69
[InstCombine] Don't mix X << Y / Z << Y with X << Y / X << Z (#69302)
Fixes #69291.
This patch improve the logic handling different patterns to avoid mixing these
pattern.
2023-10-17 18:47:49 +08:00
Simon Pilgrim
be9bc54218 [X86] vselect.ll - add vXi8 select-by-constant tests with repeated/broadcastable shuffle mask 2023-10-17 11:34:08 +01:00
Momchil Velikov
bea3684944
[AArch64] Allow only LSL to be folded into addressing mode (#69235)
There was an error in decoding shift type, which permitted shift types
other than LSL to be (incorrectly) folded into the addressing mode of a
load/store instruction.
2023-10-17 11:30:14 +01:00
Pierre van Houtryve
d2b74d7e42
[TableGen] Handle duplicate rules in combiners (#69296)
We would crash when a rule was accidentally added twice to a combiner.
This patch adds a warning instead to skip the already-processed rules.
2023-10-17 10:59:32 +02:00
Pierre van Houtryve
0841955bf3
[TableGen] Use buildConstant to emit apply pattern immediates (#66077)
Use `MachineIRBuilder::buildConstant` to emit typed immediates in
'apply' MIR patterns.
This adds flexibility, e.g. it allows us to seamlessly handle vector
cases, where a `G_BUILD_VECTOR` is needed to create a splat.
2023-10-17 10:39:59 +02:00
Zhaoxuan Jiang
041a786c78
[AArch64] Fix pairing different types of registers when computing CSRs. (#66642)
If a function has odd number of same type of registers to save, and the
calling convention also requires odd number of such type of CSRs, an FP
register would be accidentally marked as saved when producePairRegisters
returns true.

This patch also fixes the AArch64LowerHomogeneousPrologEpilog pass not
handling AArch64::NoRegister; actually this pass must be fixed along
with the register pairing so i can write a test for it.
2023-10-16 23:34:04 -07:00
Shao-Ce SUN
5a6ef95a1c
[RISCV][GISel] Add legalizer for G_UMAX, G_UMIN, G_SMAX, G_SMIN (#69150)
Similar to #67577, Lower G_UMAX, G_UMIN, G_SMAX, G_SMIN.
2023-10-17 10:36:24 +08:00
Jianjian Guan
b0eba8e209
[RISCV] Support STRICT_FP_ROUND and STRICT_FP_EXTEND when only have Zvfhmin (#68559)
This patch supports STRICT_FP_ROUND and STRICT_FP_EXTEND when we only
have Zvfhmin but no Zvfh.
2023-10-17 10:10:19 +08:00
Michael Maitland
c319c74146 [RISCV] Improve performCONCAT_VECTORCombine stride matching
If the load ptrs can be decomposed into a common (Base + Index) with a
common constant stride, then return the constant stride.
2023-10-16 16:45:26 -07:00
Michael Maitland
30ca258614 [RISCV] Pre-commit concat-vectors-constant-stride.ll
This patch commits tests that can be optimized by improving
performCONCAT_VECTORCombine to do a better job at decomposing the base
pointer and recognizing a constant offset.
2023-10-16 16:45:16 -07:00
Markus Böck
e6e62efa88
[RS4GC] Copy argument attributes from call to statepoint (#68475)
The current implementation completely ignores argument attributes on
calls, discarding them completely when creating a statepoint from a call
instruction. This is problematic in some scenarios as the argument
attributes affect the ABI of the call, leading to undefined behavior if
called with the wrong ABI attributes. Note that this cannot be solved
either by just having the function declaration annotated with the right
parameter attributes as the call might be indirect, therefore requiring
them to be present on the arguments.

This PR simply copies all parameter attributes over from the original
call to the created statepoint.
Note that some argument attributes become invalid after the lowering as
they imply memory effects that no longer hold with the statepoints.
These do not need to be explicitly handled in this PR as they are
removed by the `stripNonValidDataFromBody`.
2023-10-16 23:23:45 +02:00
Alexey Bataev
119b0f3895 Revert "[SLP]Fix PR69196: Instruction does not dominate all uses"
This reverts commit 8e2b2c4181506efc5b9321c203dd107bbd63392b to fix
a crash reported in https://lab.llvm.org/buildbot/#/builders/230/builds/19993.
2023-10-16 13:29:17 -07:00
Martin Storsjö
6f41510d4f
[llvm-rc] Accept filenames provided as multiple string literals (#68881)
GNU windres supports this, while MS rc.exe doesn't.

MS rc.exe only supports treating consecutive string literals as if they
were fused into one in a few fixed locations (most of which are already
supported), while GNU windres supports this essentially anywhere in any
string. See
b989fcbae6f179ad887d19ceef83ace1c00b87cc for one recent change that
extended support for this in one specific resource.

A reasonable use case for multiple concatenated string literals that GNU
windres accepts is `1 ICON DIR "/name.ico"`, where the directory is
provided via the preprocessor, expanding to another string literal; this
is https://github.com/llvm/llvm-project/issues/51286.

Extend the parser to try to consume all consecutive string tokens,
whenever reading a filename. Adjust the handling of user data resources
read from a file to use the readFilename() helper.

While this probably doesn't cover every single case where GNU windres
might accept concatenated string literals, this is the primary missing
case that has been reported so far.
2023-10-16 23:16:25 +03:00
Alexey Bataev
8e2b2c4181 [SLP]Fix PR69196: Instruction does not dominate all uses
During emission of the postponed gathers, need to insert them before
user instruction to avoid use before definition crash.
2023-10-16 12:57:18 -07:00