27067 Commits

Author SHA1 Message Date
Luke Lau
3927b9ab11 [VectorCombine] Add tests for unspeculatable VP binops. NFC
The current test cases to guard against speculative execution can actually be
safely speculated because the denominator is known to be not 0 or -1, and
isSafeToSpeculativelyExecuteWithOpcode will account for this. This adds some
more test cases and rejigs some existing ones to use an unknown variable
instead.
2023-10-18 14:23:02 -04:00
Oskar Wirga
c9b7d21dc5
[CFI/MergeFunctions] Modify MergeFunctions to propagate type information (#68628)
When MergeFuncs creates a thunk, it does not modify the function in
place, but creates a new one altogether. If type metadata is not
properly forwarded to this new function, LowerTypeTests will be unable
to put this thunk into the dispatch table.

The fix here is to just forward the type metadata to the newly created
functions.
2023-10-18 11:22:35 -07:00
Valery Dmitriev
c80b503496
[SLP] Improve gather tree nodes matching when users are PHIs. (#69392) 2023-10-18 09:05:11 -07:00
Florian Hahn
e7432bc343
[InstCombine] Add aligned_alloc with pointer icmp as only use. 2023-10-18 16:09:47 +01:00
Valery Dmitriev
3caccb22ab
[NFC][SLP] Test case exposing gather nodes matching deficiency affecting cost. (#69382) 2023-10-17 14:58:10 -07:00
Florian Hahn
fd31112634
[VPlan] Insert Trunc/Exts for reductions directly in VPlan.
Update the code to create Trunc/Ext recipes directly in
adjustRecipesForReductions instead of fixing it up later in
fixReductions.

This explicitly models the required conversions and also makes sure they
are generated at the right place (instead of after the exit condition),
hence the changes in a few tests.
2023-10-17 19:17:40 +01:00
Alexey Bataev
66775f8ccd [SLP]Fix PR69196: Instruction does not dominate all uses
During emission of the postponed gathers, need to insert them before
user instruction to avoid use before definition crash.
2023-10-17 10:43:59 -07:00
XChy
f2898def69
[InstCombine] Don't mix X << Y / Z << Y with X << Y / X << Z (#69302)
Fixes #69291.
This patch improve the logic handling different patterns to avoid mixing these
pattern.
2023-10-17 18:47:49 +08:00
Markus Böck
e6e62efa88
[RS4GC] Copy argument attributes from call to statepoint (#68475)
The current implementation completely ignores argument attributes on
calls, discarding them completely when creating a statepoint from a call
instruction. This is problematic in some scenarios as the argument
attributes affect the ABI of the call, leading to undefined behavior if
called with the wrong ABI attributes. Note that this cannot be solved
either by just having the function declaration annotated with the right
parameter attributes as the call might be indirect, therefore requiring
them to be present on the arguments.

This PR simply copies all parameter attributes over from the original
call to the created statepoint.
Note that some argument attributes become invalid after the lowering as
they imply memory effects that no longer hold with the statepoints.
These do not need to be explicitly handled in this PR as they are
removed by the `stripNonValidDataFromBody`.
2023-10-16 23:23:45 +02:00
Alexey Bataev
119b0f3895 Revert "[SLP]Fix PR69196: Instruction does not dominate all uses"
This reverts commit 8e2b2c4181506efc5b9321c203dd107bbd63392b to fix
a crash reported in https://lab.llvm.org/buildbot/#/builders/230/builds/19993.
2023-10-16 13:29:17 -07:00
Alexey Bataev
8e2b2c4181 [SLP]Fix PR69196: Instruction does not dominate all uses
During emission of the postponed gathers, need to insert them before
user instruction to avoid use before definition crash.
2023-10-16 12:57:18 -07:00
Yingwei Zheng
4718b4011f
[LV] Invalidate disposition of SCEV values after loop vectorization (#69230)
This PR fixes the assertion failure of `SE.verify()` after loop vectorization.
2023-10-17 03:49:39 +08:00
Florian Hahn
f7a8a78cb7
[VPlan] Also print operands of canonical IV (NFC).
Also print the operands of VPCanonicalIVPHIRecipe. That was missed
earlier.
2023-10-16 20:28:23 +01:00
Florian Hahn
38f8b7cbe4
[LV] Replace value numbers with patterns in tests (NFC).
Replace some hardcoded value numbers in CHECK-LINES to use patterns, to
 make the tests more robust wrt renumbering.
2023-10-16 19:53:44 +01:00
Nikita Popov
a72d88fb4f Revert "Reapply [Verifier] Sanity check alloca size against DILocalVariable fragment size"
This reverts commit 8840da2db237cd714d975c199d5992945d2b71e9.

This results in verifier failures during LTO, see #68929.
2023-10-16 12:17:24 +02:00
Nikita Popov
1d43096e16
[ConstraintElim] Don't decompose values wider than 64 bits (#68803)
Our coefficients are 64-bits, so adding/multiplying them can wrap in
64-bits even if there would be no wrapping the full bit width.

The alternative would be to check for overflows during all adds/muls in
decomposition. I assume that we don't particularly care about handling
wide integers here, so I've opted to bail out.

Fixes https://github.com/llvm/llvm-project/issues/68751.
2023-10-16 12:03:49 +02:00
DianQK
2ad9a65800
[LVI][CVP] Treat undef like a full range on abs(x, false) (#68711)
Fixes #68682.
2023-10-16 06:25:23 +08:00
XChy
0823cb7911
[InstCombine] Fold (X << Y) / (X << Z) -> 1 << Y >> Z (#68863)
Resolve #68857.
Alive2 proofs:
[Whole proofs](https://alive2.llvm.org/ce/z/A5b85F)
2023-10-15 22:51:45 +08:00
Yingwei Zheng
9451004987
[InstCombine][TLI] Fix function prototype of labs (#69077)
`i64 @labs(i32)` is incorrectly recognized as `LibFunc_labs` because
type ID `Long` matches both `i32` and `i64`. This PR requires the type
of argument to match the return value.

Fixes #69059.
2023-10-15 17:00:50 +08:00
XChy
b22917e6e2
[InstCombine] Fold Ext(i1) Pred shr(A, BW - 1) => i1 Pred A s< 0 (#68244)
Resolves #67916 .
This patch folds `Ext(icmp (A, xxx)) Pred shr(A, BW - 1)` into `i1 Pred
A s< 0`.
[Alive2](https://alive2.llvm.org/ce/z/k53Xwa).
2023-10-13 22:02:57 +08:00
JolantaJensen
afdb18df4d
[NFC][AArch64][LV] Reorganise LV tests using symbols from SLEEF (#68207)
The tests introduced by https://reviews.llvm.org/D134719 and later
modified in https://reviews.llvm.org/D146839 are not testing LV in
isolation. This patch:
  1. Assures that all tests test LV in isolation.
  2. Adds LV tests using llvm intrinsics that have libm mappings.

llrint, llround and lrint are not included as currently IR verifier pass
does not allow to use vector types with them.
2023-10-13 12:10:21 +01:00
zhongyunde 00443407
bf90ffb9b4 [SVE][InstCombine] Delete redundante sel instructions with ptrue
svsel(pture, x, y) => x. depend on D121792
Reviewed By: paulwalker-arm, david-arm
2023-10-13 09:20:36 +08:00
zhongyunde 00443407
127cf4ead3 [SVE][InstCombine] Precommit tests for select + ptrue 2023-10-13 09:20:36 +08:00
Noah Goldstein
2dd52b4527 [InstCombine] Improve logic for adding flags to shift instructions.
Instead of relying on constant operands, use known bits to do the
computation.

Proofs: https://alive2.llvm.org/ce/z/M-aBnw

Differential Revision: https://reviews.llvm.org/D157532
2023-10-12 16:05:19 -05:00
Noah Goldstein
968468af9c [InstCombine] Tests for adding flags to shifts; NFC
Differential Revision: https://reviews.llvm.org/D157531
2023-10-12 16:05:19 -05:00
Noah Goldstein
444383e0d0 [ValueTracking] Do more thorough non-zero check in isKnownToBePowerOfTwo when OrZero is no set.
We can cover more cases by directly checking if the result is
known-nonzero for common patterns when they are missing `OrZero`.

This patch add `isKnownNonZero` checks for `shl`, `lshr`, `and`, and `mul`.

Differential Revision: https://reviews.llvm.org/D157309
2023-10-12 16:05:19 -05:00
Leonard Chan
ef388334ee Revert "Reapply "InstCombine: Introduce SimplifyDemandedUseFPClass""
This reverts commit 5a36904c515b.

Reverted because this breaks some floating point operations. See the
comment on https://github.com/llvm/llvm-project/commit/5a36904c515b.
2023-10-12 20:23:39 +00:00
Ramkumar Ramachandra
8593c0bc02
LoopVectorize/test: clean up reduction.ll; generate using UTC (NFC) (#68890)
The test reduction.ll was introduced before utils/update_test_checks.py,
and hence contains hand-written CHECK lines. Revisit the test today, and
modernize it by:

- Removing extranous attributes on functions and their arguments, as
LoopVectorize doesn't even look at these attributes.
- Removing the target datalayout, as it is not essential for
LoopVectorize.

Finally, regenerate the CHECK lines using update_test_checks.py,
eliminating hand-written error-prone CHECK lines.
2023-10-12 15:45:15 +01:00
Antonio Frighetto
1c12dcc910 [InstCombine] Extend sext/zext boolean additions to vectors
Reported-by: shao-hua-li

Fixes: https://github.com/llvm/llvm-project/issues/68745.
2023-10-12 14:38:54 +00:00
Nikita Popov
30240e428f [PhaseOrdering] Regenerate test checks (NFC) 2023-10-12 14:40:13 +02:00
Nikita Popov
30faaaf626 [LoopVectorize] Regenerate test checks (NFC) 2023-10-12 14:35:23 +02:00
Nikita Popov
37441f1ae6 [PhaseOrdering] Add test for switch with different GEP types (NFC) 2023-10-12 14:01:58 +02:00
Alex Voicu
0ce6255a50 [HIP][LLVM][Opt] Add LLVM support for hipstdpar
This patch adds the LLVM changes needed for enabling HIP parallel algorithm offload on AMDGPU targets. What we do here is add two passes, one mandatory and one optional:

1. HipStdParAcceleratorCodeSelectionPass is mandatory, depends on CallGraphAnalysis, and implements the following transform:

    - Traverse the call-graph, and check for functions that are roots for accelerator execution (at the moment, these are GPU kernels exclusively, and would originate in the accelerator specific algorithm library the toolchain uses as an implementation detail);
    - Starting from a root, do a BFS to find all functions that are reachable (called directly or indirectly via a call- chain) and record them;
    - After having done the above for all roots in the Module, we have the computed the set of reachable functions, which is the union of roots and functions reachable from roots;
    - All functions that are not in the reachable set are removed; for the special case where the reachable set is empty we completely clear the module;

2. HipStdParAllocationInterpositionPass is optional, is meant as a fallback with restricted functionality for cases where on-demand paging is unavailable on a platform, and implements the following transform:
    - Iterate all functions in a Module;
    - If a function's name is in a predefined set of allocation / deallocation that the runtime implementation is allowed and expected to interpose, replace all its uses with the equivalent accelerator aware function, iff the latter is available;
        - If the accelerator aware equivalent is unavailable we warn, but compilation will go ahead, which means that it is possible to get issues around the accelerator trying to access inaccessible memory at run time;
    - We rely on direct name matching as opposed to using the new alloc-kind family of attributes and / or the LibCall analysis pass because some of the legacy functions that need replacing would not carry the former or be identified by the latter.

Reviewed by: JonChesterfield, yaxunl

Differential Revision: https://reviews.llvm.org/D155856
2023-10-12 11:26:48 +01:00
Yingwei Zheng
8a7e547798
[InstCombine] Canonicalize (X +/- Y) & Y into ~X & Y when Y is a power of 2 (#67915)
This patch canonicalizes the pattern `(X +/- Y) & Y` into `~X & Y` when `Y` is a power of 2 or zero.
It will reduce the patterns to match in #67836 and exploit more optimization opportunities.
Alive2: https://alive2.llvm.org/ce/z/LBpvRF
2023-10-12 17:18:12 +08:00
Oskar Wirga
b48450c209
[MergeFuncs] Use sizeWithoutDebug to decide if we create a thunk (#68627)
I noticed that when we determine the size of the function to figure out
if its profitable, we include debug instructions which can end up making
larger functions than necessary.
2023-10-11 17:32:41 -07:00
Nikita Popov
2b74db6c9b [ConstraintElim] Add test for #68751 (NFC) 2023-10-11 15:52:46 +02:00
Paul Walker
6383785bad
[SVE][CodeGenPrepare] Sink address calculations that match SVE gather/scatter addressing modes. (#66996)
SVE supports scalar+vector and scalar+extw(vector) addressing modes.
However, the masked gather/scatter intrinsics take a vector of
addresses, which means address computations can be hoisted out of
loops.  The is especially true for things like offsets where the
true size of offsets is lost by the time you get to code generation.

This is problematic because it forces the code generator to legalise
towards `<vscale x 2 x ty>` vectors that will not maximise bandwidth
if the main block datatypes is in fact i32 or smaller.

This patch sinks GEPs and extends for cases where one of the above
addressing modes can be used.

NOTE: There are cases where it would be better to split the extend
in two with one half hoisted out of a loop and the other within the
loop.  Whilst true I think this switch of default is still better
than before because the extra extends are an improvement over being
forced to split a gather/scatter.
2023-10-11 13:20:08 +01:00
Alex Voicu
25935c384d Revert "[HIP][LLVM][Opt] Add LLVM support for hipstdpar"
This reverts commit c5bba7ea5a05f540948f76a189c880eb24a5e8c6.
2023-10-11 12:27:03 +01:00
Alex Voicu
c5bba7ea5a [HIP][LLVM][Opt] Add LLVM support for hipstdpar
This patch adds the LLVM changes needed for enabling HIP parallel algorithm offload on AMDGPU targets. What we do here is add two passes, one mandatory and one optional:

1. HipStdParAcceleratorCodeSelectionPass is mandatory, depends on CallGraphAnalysis, and implements the following transform:

    - Traverse the call-graph, and check for functions that are roots for accelerator execution (at the moment, these are GPU kernels exclusively, and would originate in the accelerator specific algorithm library the toolchain uses as an implementation detail);
    - Starting from a root, do a BFS to find all functions that are reachable (called directly or indirectly via a call- chain) and record them;
    - After having done the above for all roots in the Module, we have the computed the set of reachable functions, which is the union of roots and functions reachable from roots;
    - All functions that are not in the reachable set are removed; for the special case where the reachable set is empty we completely clear the module;

2. HipStdParAllocationInterpositionPass is optional, is meant as a fallback with restricted functionality for cases where on-demand paging is unavailable on a platform, and implements the following transform:
    - Iterate all functions in a Module;
    - If a function's name is in a predefined set of allocation / deallocation that the runtime implementation is allowed and expected to interpose, replace all its uses with the equivalent accelerator aware function, iff the latter is available;
        - If the accelerator aware equivalent is unavailable we warn, but compilation will go ahead, which means that it is possible to get issues around the accelerator trying to access inaccessible memory at run time;
    - We rely on direct name matching as opposed to using the new alloc-kind family of attributes and / or the LibCall analysis pass because some of the legacy functions that need replacing would not carry the former or be identified by the latter.

Reviewed by: JonChesterfield, yaxunl

Differential Revision: https://reviews.llvm.org/D155856
2023-10-11 12:22:00 +01:00
Florian Hahn
56a3e49a00
[ConstraintElim] Support decrementing inductions with step -1. (#68644)
Extend the logic in addInfoForInductions to support decrementing
inductions with a step of -1.

Fixes #64881.
2023-10-10 09:37:27 -07:00
Sergey Kachkov
9f12f655c4
[GVN] Drop Clobber dependency if store may overwrite only the same value (#68322)
In some cases clobbering store can be safely skipped if it can only must
or no alias with memory location and it writes the same value. This
patch supports simple case when the value from memory location was
loaded in the same basic block before the store and there are no
modifications between them.
2023-10-10 19:22:00 +03:00
Sergey Kachkov
9ce8103e87 [GVN][NFC] Add pre-commit test 2023-10-10 19:07:38 +03:00
Alex Voicu
98eda5dda7 Revert "[HIP][LLVM][Opt] Add LLVM support for hipstdpar" in order to address build breakage.
This reverts commit 9b98ebb0eb43b005921926a622177f10e13b1ac6.
2023-10-10 12:16:10 +01:00
Alex Voicu
9b98ebb0eb [HIP][LLVM][Opt] Add LLVM support for hipstdpar
This patch adds the LLVM changes needed for enabling HIP parallel algorithm offload on AMDGPU targets. What we do here is add two passes, one mandatory and one optional:

1. HipStdParAcceleratorCodeSelectionPass is mandatory, depends on CallGraphAnalysis, and implements the following transform:

    - Traverse the call-graph, and check for functions that are roots for accelerator execution (at the moment, these are GPU kernels exclusively, and would originate in the accelerator specific algorithm library the toolchain uses as an implementation detail);
    - Starting from a root, do a BFS to find all functions that are reachable (called directly or indirectly via a call- chain) and record them;
    - After having done the above for all roots in the Module, we have the computed the set of reachable functions, which is the union of roots and functions reachable from roots;
    - All functions that are not in the reachable set are removed; for the special case where the reachable set is empty we completely clear the module;

2. HipStdParAllocationInterpositionPass is optional, is meant as a fallback with restricted functionality for cases where on-demand paging is unavailable on a platform, and implements the following transform:
    - Iterate all functions in a Module;
    - If a function's name is in a predefined set of allocation / deallocation that the runtime implementation is allowed and expected to interpose, replace all its uses with the equivalent accelerator aware function, iff the latter is available;
        - If the accelerator aware equivalent is unavailable we warn, but compilation will go ahead, which means that it is possible to get issues around the accelerator trying to access inaccessible memory at run time;
    - We rely on direct name matching as opposed to using the new alloc-kind family of attributes and / or the LibCall analysis pass because some of the legacy functions that need replacing would not carry the former or be identified by the latter.

Reviewed by: JonChesterfield, yaxunl

Differential Revision: https://reviews.llvm.org/D155856
2023-10-10 12:02:05 +01:00
Nikita Popov
32ec6d91a1
[SCEV] Make invalidation in SCEVCallbackVH more thorough (#68316)
When a SCEVCallbackVH is RAUWed, we currently do a def-use walk and
remove dependent instructions from the ValueExprMap. However, unlike
SCEVs usual invalidation, this does not forget memoized values.

The end result is that we might end up removing a SCEVUnknown from the
map, while that expression still has users. Due to that, we may later
fail to invalide those expressions. In particular, invalidation of loop
dispositions only does something if there is an expression for the
value, which would not be the case here.

Fix this by using the standard forgetValue() API, instead of rolling a
custom variant.

Fixes https://github.com/llvm/llvm-project/issues/68285.
2023-10-10 10:55:57 +02:00
DianQK
81857940f2
[LVI][CVP] Treat undef like a full range (#68190)
When converting to ConstantRange, we should treat undef like a full range.
Fixes #68381.
2023-10-10 16:03:24 +08:00
Alexey Bataev
c2ae16f6a7 [VectorCombine]Fix a crash during long vector analysis.
If the analysis of the single vector requested, need to use original
type to avoid crash
2023-10-09 14:22:37 -07:00
Allen
ea86fb8caf
[InstCombine] Fold zext-of-icmp with no shift (#68503)
This regression triggers after commit f400daa to fix infinite loop
issue.

In this case, we can known the shift count is 0, so it will not be
triggered by the form of (iN (~X) u>> (N - 1)) in commit 21d3871, of
which N indicates the data type bitwidth of X.

Fixes https://github.com/llvm/llvm-project/issues/68465.
2023-10-09 23:46:09 +08:00
zhongyunde 00443407
e44cfe0fb1 [InstCombine] Precommit test for PR68465 2023-10-09 23:39:09 +08:00
Rin
df8e0d057d
[AArch64][LoopVectorize] Use upper bound trip count instead of the constant TC when choosing max VF (#67697)
This patch is based off of
https://github.com/llvm/llvm-project/pull/67543.

We are currently using the exact trip count to make decisions regarding
the maximum VF. We can instead use the upper bound TC, which will be the
same as the constant trip count when that is known.
2023-10-09 16:26:19 +01:00