This PR enables the use of the status register in inline assembly.
This is necessary to, for example, set and retrieve the current
interrupt mask.
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Co-authored-by: kirk <knickish@gmail.com>
Had been doing this piece by piece, but makes more sense to do it in a
single PR. Adds support for `ARID`, `PCI`, `PCD`, `AL`, and `ARD`
addressing modes for atomic operations, along with a variety of tests.
The `CodeModel` tests have been rearranged, as some of the new
addressing modes are only exercised under some combinations of
`CodeModel` and relocation mode
Including splitting up the FPCR register class into classes with finer
granularities.
Right now we only support address / data registers as source /
destinations.
This reduces dependencies on `llvm-tblgen` so much.
`CodeGenTypes` depends on `Support` at the moment.
Be careful to append deps on this, since Targets' tablegens
depend on this.
Depends on D149024
Differential Revision: https://reviews.llvm.org/D148769
This is rework of;
- D30046 (LLT)
Since I have introduced `llvm-min-tblgen` as D146352, `llvm-tblgen`
may depend on `CodeGen`.
`LowLevlType.h` originally belonged to `CodeGen`. Almost all userse are
still under `CodeGen` or `Target`. I think `CodeGen` is the right place
to put `LowLevelType.h`.
`MachineValueType.h` may be moved as well. (later, D149024)
I have made many modules depend on `CodeGen`. It is consistent but
inefficient. It will be split out later, D148769
Besides, I had to isolate MVT and LLT in modmap, since
`llvm::PredicateInfo` clashes between `TableGen/CodeGenSchedule.h`
and `Transforms/Utils/PredicateInfo.h`.
(I think better to introduce namespace llvm::TableGen)
Depends on D145937, D146352, and D148768.
Differential Revision: https://reviews.llvm.org/D148767
- FP registers and register classes definitions
- MC support for FP registers
- MC support for the FPDR -> FPDR variant of FMOVE/FSMOVE/FDSMOVE
Note that we don't implement 32/64-bit FP registers with subregisters since
f32/f64 values will be converted to f80 upon storing into a register,
rather than occupying part of the register.
So we only use register classes with different value types to distinguish
them.
Differential Revision: https://reviews.llvm.org/D147480
32-bit immediates require special cares because they go across the
normal word (16 bits) boundaries.
This patch also fixes some incorrect disassembler test cases.
Differential Revision: https://reviews.llvm.org/D142080
This is an example usage of D120958.
After these patches are landed, we can strip off the codebeads officially.
Reviewed By: myhsu
Differential Revision: https://reviews.llvm.org/D120960
This moves the registry higher in the LLVM library dependency stack.
Every client of the target registry needs to link against MC anyway to
actually use the target, so we might as well move this out of Support.
This allows us to ensure that Support doesn't have includes from MC/*.
Differential Revision: https://reviews.llvm.org/D111454
When reading 32 bits a 32-bit shift would be executed.
This is undefined behaviour, but in this case we can just replace the
entire scratch value to avoid it.
Differential Revision: https://reviews.llvm.org/D110769
M68kDisassembler should put M68kDesc as its direct library dependency
since it uses logics releated to code beads Otherwise the build will
fail when building LLVM libraries as shared objects (building LLVM
libraries statically won't have this problem though)
