7 Commits

Author SHA1 Message Date
Ami-zhang
1897bf61f0
[LoongArch] Enable FeatureExtLSX for generic-la64 processor (#113421)
This commit makes the `generic` target to support FP and LSX, as
discussed in #110211. Thereby, it allows 128-bit vector to be enabled by
default in the loongarch64 backend.
2024-10-31 15:58:15 +08:00
Florian Hahn
53266f73f0
[VPlan] Run DCE after unrolling.
This cleans up a number of dead recipes after unrolling if only their
first or last parts are used. This simplifies a number of tests.

Fixes https://github.com/llvm/llvm-project/issues/109581.
2024-09-22 22:08:46 +01:00
Zhaoxin Yang
89d1eb6734
[LoongArch] Remove experimental auto-vec feature. (#100070)
Currently, automatic vectorization will be enabled with `-mlsx/-mlasx`
enabled.
2024-07-23 15:19:00 +08:00
Jay Foad
d4a0154902
[llvm-project] Fix typo "seperate" (#95373) 2024-06-13 20:20:27 +01:00
hev
1e86e92428
[LoongArch] Enable interleaved vectorization (#92629)
This PR enables interleaved vectorization for LoongArch, with a default
interleaving factor of `2`.
2024-05-21 15:31:02 +08:00
wanglei
1e7763557b
[LoongArch] Add support for getNumberOfRegisters() (#88372)
The `TTI` hooks are used during vectorization for calculating register
pressure. The default implementation defined wrong value for register
number (all register class are 8 registers).

This patch also defines LoongArch's own register classes.
2024-04-12 16:15:02 +08:00
wanglei
fcff4582f0
[LoongArch] Permit auto-vectorization using LSX/LASX with auto-vec feature (#78943)
With enough codegen complete, we can now correctly report the size of
vector registers for LSX/LASX, allowing auto vectorization (The
`auto-vec` feature needs to be enabled simultaneously).

As described, the `auto-vec` feature is an experimental one. To ensure
that automatic vectorization is not enabled by default, because the
information provided by the current `TTI` cannot yield additional
benefits for automatic vectorization.
2024-01-23 09:06:35 +08:00