27 Commits

Author SHA1 Message Date
Kazu Hirata
0575815b70
[TableGen] Avoid repeated hash lookups (NFC) (#120681) 2024-12-20 10:28:58 -08:00
Kazu Hirata
5b5b241edf
[TableGen] Avoid repeated hash lookups (NFC) (#120619) 2024-12-19 13:02:55 -08:00
Kazu Hirata
b0a4b5b35a
[TableGen] Avoid repeated hash lookups (NFC) (#120532) 2024-12-19 08:00:02 -08:00
Sergei Barannikov
97c3c32372
[TableGen][SystemZ] Correctly check the range of a leaf immediate (#119931)
The "Size >= 32" check probably dates back to when TableGen integers
were 32-bit. Delete it and simplify code by using `isInt`/`isUInt`.
2024-12-14 13:58:23 +03:00
Sergei Barannikov
d1f51c67fd
[TableGen] Add TreePatternNode::children and use it in for loops (NFC) (#119877) 2024-12-13 22:05:57 +03:00
abhishek-kaushik22
31ce47b5d6
[TableGen] Use std::move to avoid copy (#113061) 2024-11-21 11:48:46 -08:00
Yingwei Zheng
c727b48287
[SDAG][ISel][TableGen][LoongArch] Report error for trivial bitcasts when there are predicate calls (#116075)
On loongarch64 with lsx extension, we select `VBITREV_W` for `v4i32 (xor
X, (shl splat(1), Y))`:

8e66303916/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td (L1583-L1584)

And `vsplat_imm_eq_1` is defined as:

8e66303916/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td (L77-L87)

For the `(bitconvert (v4i32 (build_vector)))` case, the pattern is
expected to be:
```
PATTERN: (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vj, (shl:{ *:[v4i32] } (bitconvert:{ *:[v4i32] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplat_imm_eq_1>>, v4i32:{ *:[v4i32] }:$vk))
RESULT:  (VBITREV_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vj, v4i32:{ *:[v4i32] }:$vk)
```

However, `simplifyTree` drops the `bitconvert` node and its predicates:

8e66303916/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp (L3036-L3062)

Then llvm will match `vsplat_imm_eq_1` for any v4i32 splats and cause a
miscompilation:
```
PATTERN: (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vj, (shl:{ *:[v4i32] } (build_vector:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$vk))
RESULT:  (VBITREV_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vj, v4i32:{ *:[v4i32] }:$vk)
```

This patch adds additional checks for predicates associated with the
trivial bitconvert node. Unused patterns in the LoongArch target are
also removed.

Fixes https://github.com/llvm/llvm-project/issues/116008.
2024-11-19 21:24:40 +08:00
Sergei Barannikov
501a583441
[TableGen][SelectionDAG] Remove the implicit DAG node (#115295)
The node was introduced in 59c39dc1 and was intended to allow writing
patterns like this:
`[(set AL, (mul AL, GR8:$src1)), (implicit EFLAGS)]`

However, it does not introduce new functionality because the same
pattern can be equivalently expressed as:
`[(set AL, EFLAGS, (mul AL, GR8:$src1))]`

The latter form is also more flexible as it allows reordering output
operands.

In most places uses of `implicit` were redundant -- removing them didn't
change anything in the generated DAG tables. The only three cases where
it did have effect are in X86InstrArithmetic.td and X86InstrSystem.td --
those were rewritten to use `set` node.

Removing `implicit` from some patterns made them importable by GISel,
hence the change in a test.
2024-11-09 07:25:40 +03:00
Jessica Clarke
9467645547
[CodeGen] Rename MVT::iPTRAny to MVT::pAny
Whilst in upstream LLVM iPTRAny is only ever an integer, essentially an
alias for iPTR, this is not true in CHERI LLVM, where it gets used to
mean "iPTR or cPTR", i.e. either an integer address or a capability
(with cPTR and cN being the capability equivalents of iPTR and iN).
Moreover, iPTRAny is already not itself regarded as an integer (calling
isInteger() will give false), so the "i" prefix is misleading, and it
stands out as different from all the other xAny that have a single
letter prefix denoting their type.

Thus, rename it to pAny, reflecting that it is an overloaded pointer
type, which could end up being specialised to an integer type, but does
not have to be.

This has been verified to have no effect on the generated files for LLVM
itself or any in-tree target beyond the replacement of the identifier
iPTRAny with pAny in GenVT.inc.

Reviewers: arsenm

Reviewed By: arsenm

Pull Request: https://github.com/llvm/llvm-project/pull/113733
2024-10-30 03:27:48 +00:00
Jessica Clarke
e8b7f53fa4
[TableGen] Remove a pointless check for iPTRAny
We've already called EnforceInteger on Types[0], and iPTRAny isn't
regarded as an integer type (note that TableGen special-cases iPTR here
to include that, though), so we cannot possibly still have an iPTRAny by
this point. Delete the check, and let getFixedSizeInBits catch it along
with all the other overloaded types if that ever becomes false. Also
document why we have this check whilst here.

Reviewers: arsenm

Reviewed By: arsenm

Pull Request: https://github.com/llvm/llvm-project/pull/113732
2024-10-30 03:19:53 +00:00
Rahul Joshi
62e2c7fb2d
[LLVM][TableGen] Change all Init pointers to const (#112705)
This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-10-18 07:50:22 -07:00
Rahul Joshi
d256b9e88b
[TableGen] Change DefInit::Def to a const Record pointer (#110747)
This change undoes a const_cast<> introduced in an earlier change to
help transition to const pointers. It is a part of effort to have better
const correctness in TableGen backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-10-02 09:48:26 -07:00
Stephen Chou
ec61311e77
[LLVM][TableGen] Support type casts of nodes with multiple results (#109728)
Currently, type casts can only be used to pattern match for intrinsics
with a single overloaded return value. For instance:
```
def int_foo : Intrinsic<[llvm_anyint_ty], []>;
def : Pat<(i32 (int_foo)), ...>;
```

This patch extends type casts to support matching intrinsics with
multiple overloaded return values. As an example, the following defines
a pattern that matches only if the overloaded intrinsic call returns an
`i16` for the first result and an `i32` for the second result:
```
def int_bar : Intrinsic<[llvm_anyint_ty, llvm_anyint_ty], []>;
def : Pat<([i16, i32] (int_bar)), ...>;
```
2024-10-01 11:17:00 +04:00
Rahul Joshi
3138eb500c
[LLVM][TableGen] Use const record pointers in TableGen/Common files (#109467)
Use const record pointers in TableGen/Common files.

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-23 13:07:31 -07:00
Rahul Joshi
87e8b53009
[LLVM][TableGen] Change CodeGenDAGPatterns to use const RecordKeeper (#108762)
Change CodeGenDAGPatterns to use const RecordKeeper.

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-15 10:26:03 -07:00
Rahul Joshi
3786568196
[TableGen] Change CodeGenInstruction record members to const (#107921)
Change CodeGenInstruction::{TheDef, InfereredFrom} to const pointers.

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-11 08:52:26 -07:00
Rahul Joshi
bdf02249e7
[TableGen] Change CGIOperandList::OperandInfo::Rec to const pointer (#107858)
Change CGIOperandList::OperandInfo::Rec and CGIOperandList::TheDef to
const pointer.

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-09 14:33:21 -07:00
Rahul Joshi
ce3c58e104
[NFC][TableGen] Replace DefInit::get() with Record::getDefInit() (#107762)
Eliminate DefInit::get() as its a duplicate of Record::getDefInit(). 
Use early return in `VarDefInit::instantiate`.
2024-09-08 12:18:53 -07:00
Rahul Joshi
0ceffd362b
[TableGen] Add PrintError family overload that take a print function (#107333)
Add PrintError and family overload that accepts a print function. This
avoids constructing potentially long strings for passing into these
print functions.
2024-09-07 05:13:54 -07:00
Rahul Joshi
660cc98647
[TableGen] Add CodeGenIntrinsicsMap for on-demand intrinsic creation (#107100)
- Add class `CodeGenIntrinsicMap` for on-demand creation of  
  `CodeGenIntrinsic`.
- Add class `CodeGenIntrinsicContext` to capture global information
  required to build `CodeGenIntrinsic` objects.
- Adopt GlobalISel PatternParser and SearchableTableEmitter to use it.
2024-09-04 14:58:01 -07:00
Kazu Hirata
d9293519bc
[TableGen] Use llvm::unique (NFC) (#94163) 2024-06-02 11:52:12 -07:00
jofrn
d0dc29c208
[TableGen] HasOneUse builtin predicate on PatFrags (#91578)
This predicate tells GlobalISelEmitter and DAGISelEmitter to check that
the instruction to emit has only one use of its result. This can be used
on a PatFrag instead of defining custom predicates for both emitters per
record that requires it.
2024-05-20 06:18:49 -08:00
Jay Foad
ace3bd0580 Revert "[TableGen] Ignore inaccessible memory when checking pattern flags (#90061)"
This reverts commit 6578356a4e3e6acd7983c74feab43ac96925894c.

The patch had no effect due to a silly mistake and fixing the mistake
causes other problems.
2024-04-26 14:49:36 +01:00
Jay Foad
6578356a4e
[TableGen] Ignore inaccessible memory when checking pattern flags (#90061)
In the AMDGPU backend we have some cases where we'd like to mark an
intrinsic as IntrInaccessibleMemOnly to model dependencies, but the
corresponding MachineInstrs use uses/defs of a special physical register
to express the same thing. In this case TableGen would complain:

  Pattern doesn't match mayLoad/mayStore = 0

but the error is not useful.
2024-04-26 10:28:52 +01:00
jofrn
eae7554d3f
[TableGen] ShouldIgnore Pattern bit to disable DAG pattern imports during GISel (#88382)
Added GISelShouldIgnore property to class Pattern in TargetSelectionDAG.td; it's similar to FastISelShouldIgnore. This bit can be put on a record to avoid its pattern import within GlobalISelEmitter. This allows one to avoid the record's GISel .td implementation, .inc generation, and any skipped pattern warnings from -warn-on-skipped-patterns.
2024-04-25 16:42:48 -04:00
Shilei Tian
cfadf3f622
[TableGen] Fix a potential crash when operand doesn't appear in the instruction pattern (#87663)
We have a check of whether an operand is in the instruction pattern, and
emit an
error if it is not, but we simply continue execution, including directly
dereferencing a point-like object `InVal`, which will be just created
when
accessing the map. It contains a `nullptr` so dereferencing it causes
crash.
This is a very trivial fix.
2024-04-04 20:29:26 -04:00
Pierre van Houtryve
fa3d789df1
[RFC][TableGen] Restructure TableGen Source (#80847)
Refactor of the llvm-tblgen source into:
- a "Basic" library, which contains the bare minimum utilities to build
`llvm-min-tablegen`
- a "Common" library which contains all of the helpers for TableGen
backends. Such helpers can be shared by more than one backend, and even
unit tested (e.g. CodeExpander is, maybe we can add more over time)

Fixes #80647
2024-03-25 09:40:35 +01:00