230433 Commits

Author SHA1 Message Date
Nathan Chancellor
4e0008dcbe
Revert "[InstCombine] try to narrow shifted bswap-of-zext"
This reverts commit 9e9bda2e8f5b88715bad767a4b7740df32b040d2.

This causes a backend error when building the Linux kernel for arm64.
See https://reviews.llvm.org/D122166 for a simplified reproducer.
2022-03-22 17:32:33 -07:00
Vasileios Porpodas
27bd8f9492 Recommit "[SLP] Fix lookahead operand reordering for splat loads." attempt 2, fixed assertion crash.
Original review: https://reviews.llvm.org/D121354

This reverts commit f7d7d2a08d16356c57f6d2d36bc2fc0589a55df9.
2022-03-22 16:41:55 -07:00
Arthur Eubanks
e22b78de27 [gn build] Manually port 89f6b26 2022-03-22 16:26:44 -07:00
Snehasish Kumar
27a4f2545f Reland "[memprof] Store callsite metadata with memprof records."
This reverts commit f4b794427e8037a4e952cacdfe7201e961f31a6f.

Reland with underlying msan issue fixed in D122260.
2022-03-22 14:40:02 -07:00
Snehasish Kumar
61c75eb637 [memprof] Initialize MemInfoBlock data.
This patch updates the existing default no-arg constructor for
MemInfoBlock to explicitly initialize all members. Also add missing
DataTypeId initialization to the other constructor. These issues were
exposed by msan on patch D121179. With this patch D121179 builds cleanly
on msan.

Reviewed By: tejohnson

Differential Revision: https://reviews.llvm.org/D122260
2022-03-22 14:35:57 -07:00
Craig Topper
9933015fdd [X86] Fold MMX_MOVD64from64rr + store to MMX_MOVQ64mr instead of MMX_MOVD64from64mr.
MMX_MOVD64from64rr moves an MMX register to a 64-bit GPR.

MMX_MOVD64from64mr is the memory version of moving a MMX register to a
64-bit GPR. It requires the REX.W bit to be set. There are no isel
patterns that use this instruction.

MMX_MOVQ64mr is the MMX register store instruction. It doesn't
require a REX.W prefix. This makes it one byte shorter to encode
than MMX_MOVD64from64mr in many cases.

Both store instructions output the same mnemonic string. The assembler
would choose MMX_MOVQ64mr if it was to parse the output. Which is
another reason using it is the correct thing to do.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D122241
2022-03-22 14:21:55 -07:00
Craig Topper
73f0af106b [SelectionDAG] Add printing support for the Align value of AssertAlign nodes.
Differential Revision: https://reviews.llvm.org/D122262
2022-03-22 14:16:32 -07:00
Mike Rice
2cedaee6f7 [OpenMP] Initial parsing/sema for the 'omp parallel loop' construct
Adds basic parsing/sema/serialization support for the
  #pragma omp parallel loop directive.

 Differential Revision: https://reviews.llvm.org/D122247
2022-03-22 13:55:47 -07:00
Stanislav Mekhanoshin
72c1a0d9c2 [AMDGPU] Allow v_accvgpr_write to use SGPR on gfx90a
This is undocumented, but it should work.

Differential Revision: https://reviews.llvm.org/D122252
2022-03-22 13:52:29 -07:00
Philip Reames
7abefc4222 [instcombine] Fold away memset/memmove from otherwise unused alloca
The motivation for this is that while both memcpyopt and dse will catch this case, both are limited by MSSA's walk back threshold when finding clobbers.  As such, if you have a memcpy of an otherwise dead alloca placed towards the end of a long basic block with lots of other memory instructions, it would be missed.  This is a bit undesirable for such an "obviously" useless bit of code.

As noted in comments, we should probably generalize instcombine's escape analysis peephole (see visitAllocInst) to allow read xor write.  Doing that would subsume this code in a more general way, but is also a more involved change.  For the moment, I went with the easiest fix.
2022-03-22 13:48:48 -07:00
Arthur Eubanks
f7d7d2a08d Revert "Recommit "[SLP] Fix lookahead operand reordering for splat loads.""
This reverts commit 79613185d305013de743cdbd6690e4d77c8af27e.

Causes crashes, see comments in https://reviews.llvm.org/D121973.
2022-03-22 13:33:49 -07:00
Sanjay Patel
ccf8c969c2 [InstCombine] reorder code, fix formatting; NFC
The affected code can be updated to solve #54364,
so make some cosmetic diffs before real changes.
2022-03-22 16:33:01 -04:00
Philip Reames
57d02900b5 [test,instcombine] Precommit test for upcoming transform 2022-03-22 13:21:09 -07:00
Stanislav Mekhanoshin
631a643940 [AMDGPU] Update mfma test to run gfx940 checks. NFC. 2022-03-22 12:43:57 -07:00
Philip Reames
03949165cd [test] Autogen a test for ease of update 2022-03-22 12:41:23 -07:00
David Blaikie
4841dab4af llvm-dwarfdump: Including calling convention attribute in pretty printed type names 2022-03-22 19:19:54 +00:00
David Blaikie
a3095a25d0 DebugInfo: Simplify const/volatile printing for function types 2022-03-22 19:19:54 +00:00
Aaron Ballman
a6beb18b84 Revert "Add UTF32 to/from UTF8 conversion functions"
This reverts commit c3460689288abc98c91d8d6bffa74be9eb16c74d.

It broke at least one of the builders:
https://lab.llvm.org/buildbot#builders/100/builds/13947
2022-03-22 15:00:40 -04:00
Marcus Johnson
c346068928 Add UTF32 to/from UTF8 conversion functions
This is anticipated to be used in new format specifier checking code.
2022-03-22 13:41:43 -04:00
Simon Pilgrim
7f8572b8c3 [ARM] select_xform.ll - re-add and fix missing CHECK prefixes
We were still checking test results with the CHECK prefix but they had bit-rotted since whenever it'd been removed from the --check-prefixes list
2022-03-22 17:35:10 +00:00
Craig Topper
51940d69cb [RISCV] Special case sign extended scalars when type legalizing nxvXi64 .vx instrinsics on RV32.
On RV32, we need to type legalize i64 scalar arguments to intrinsics.
We usually do this by splatting the value into a vector separately.
If the scalar happens to be sign extended, we can continue using a .vx
intrinsic.

We already special cased sign extended constants, this extends it
to any sign extended value.

I've only added tests for one case of vadd. Most intrinsics go
through the same check.

Reviewed By: khchen

Differential Revision: https://reviews.llvm.org/D122186
2022-03-22 10:29:06 -07:00
Craig Topper
9b0f227d7b [TableGen][RISCV] Add InstAliases with zero_reg to cover unmasked vnot.v, vncvt.x.x.w, vneg.v, etc.
The mask being NoRegister prevented the existing aliases from matching
since NoRegister isn't in the VMV0 register class.

To workaround this I've added new aliases that look for zero_reg.
I had to motify tablegen to generate matching code for zero_reg.
And as a consequence, I had to change the EmitPriority for an ARM
alias that used zero_reg that started printing.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D121496
2022-03-22 10:14:43 -07:00
Zakk Chen
23d60ce164 [RISCV][NFC] Refine and refactor RISCVVEmitter and riscv_vector.td.
1. Rename nomask as unmasked to keep with the terminology in the spec.
2. Merge UnMaskpolicy and Maskedpolicy arguments into one in RVVBuiltin class.
3. Rename HasAutoDef as HasBuiltinAlias.
4. Move header definition code into one class.

Reviewed By: rogfer01

Differential Revision: https://reviews.llvm.org/D120870
2022-03-22 09:58:43 -07:00
Craig Topper
49c2206b3b [VP] Preserve address space of pointer for strided load/store intrinsics.
This adds LLVMAnyPointerToElt to use instead of LLVMPointerToElt.
This allows us to preserve the address space as part of the type
overload for the intrinsic, but still require the vector element
type to match the pointer type.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D122042
2022-03-22 09:52:54 -07:00
Nathan Sidwell
c354167ae2 [demangler] Add support for C++20 modules
Add support for module name demangling.  We have two new demangler
nodes -- ModuleName and ModuleEntity. The former represents a module
name in a hierarchical fashion. The latter is the combination of a
(name) node and a module name. Because module names and entity
identities use the same substitution encoding, we have to adjust the
flow of how substitutions are handled, and examine the substituted
node to know how to deal with it.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D119933
2022-03-22 09:42:52 -07:00
Hendrik Greving
510a2bbda4 [IR] Allow matching pointer to vector with opaque pointers.
Allows for skipping the pointer to vector type if opaque pointers
are enabled and the matching pointer is a vector pointer when
matching an intrinsic signature in the verifier.

No test added since lacking a target using intrinsic with pointer
to vector arguments.

Differential Revision: https://reviews.llvm.org/D122203
2022-03-22 09:34:48 -07:00
Alex Bradbury
ef9cf86eb0 [WebAssembly][NFC] Delete type checking logic for removed ref.null instruction
D114979 changed the textual formal of ref.null - dropping ref.null in
favour of ref.null_extern and ref.null_func. Therefore, the type checker
no longer needs logic to handle "ref.null".

Differential Revision: https://reviews.llvm.org/D122123
2022-03-22 16:24:05 +00:00
Alex Bradbury
9001168cf8 [WebAssembly] Add tests for the Asm type checker
While looking at bugs like PR54022, I noted that there is no real test
coverage for the asm type checker. This patch starts to address that,
adding a series of tests for the errors messages produced, as well as
some FIXMEs as an XFAIL test for some current issues.

It's not intended to be an exhaustive test, but does have test cases for
each of the instructions that the type checker has specific handling
for.

Differential Revision: https://reviews.llvm.org/D122020
2022-03-22 16:13:35 +00:00
Zakk Chen
10fd2822b7 [RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR
intrinsics.

Those operations are updated under a tail agnostic policy, but they
could have mask agnostic or undisturbed.

Reviewed By: rogfer01

Differential Revision: https://reviews.llvm.org/D120228
2022-03-22 07:47:21 -07:00
Sanjay Patel
c4d74a93f6 [InstCombine] add test for abs with dominating condition; NFC
There's a potential miscompile or missed optimization with
propagating 'nsw' in the transform proposed in D122013, so
we need at least one more test for coverage.
2022-03-22 10:42:52 -04:00
chenglin.bi
01a2ba5dfb [InstCombine] add tests for abs with dominating condition; NFC
Baseline tests for D122013 (issue #54132).
2022-03-22 10:37:12 -04:00
Florian Hahn
50c8588e44
[LV] Remove Loop argument from createInductionResumeValues (NFCI).
createInductionResumeValues only uses its loop argument only to get the
pre-header, but the pre-header is already known (we created/cached it
earlier). Remove the unneeded loop argument.
2022-03-22 14:23:12 +00:00
Joseph Huber
5856f30b5a [LTO] Add configuartion option to use default optimization pipeline
This patch adds a configuration option to simply use the default pass
pipeline in favor of the LTO-specific one. We observed some severe
performance penalties when uding device-side LTO for OpenMP offloading
applications caused by the LTO-pass pipeline. This is primarily because
OpenMP uses an LLVM bitcode library to implement a GPU runtime library.
In a standard compilation we link this bitcode library into each source
file and optimize it with the default pipeline. When performing LTO we
link it late with all the files, but the bitcode library never has the
regular optimization pipeline applied to it so we miss a few
optimizations just using the LTO pipeline to optimize it.

I'm not committed to this solution, but it's the easiest method to solve
this performance regression when using LTO without changing the
optimizatin pipeline for other users.

Reviewed By: tianshilei1992

Differential Revision: https://reviews.llvm.org/D122133
2022-03-22 09:28:45 -04:00
Sanjay Patel
60820e53ec [InstCombine] try to canonicalize logical shift after bswap
When shifting by a byte-multiple:
bswap (shl X, C) --> lshr (bswap X), C
bswap (lshr X, C) --> shl (bswap X), C

This is an IR implementation of a transform suggested in D120648.
The "swaps cancel" test models the motivating optimization from
that proposal.

Alive2 checks (as noted in the other review, we could use
knownbits to handle shift-by-variable-amount, but that can be an
enhancement patch):
https://alive2.llvm.org/ce/z/pXUaRf
https://alive2.llvm.org/ce/z/ZnaMLf

Differential Revision: https://reviews.llvm.org/D122010
2022-03-22 09:10:55 -04:00
Djordje Todorovic
91ea247039 [Debugify] Use DebugifyLevel in Debugify original mode
Before this patch the DebugifyLevel option was used for
the synthetic mode, so after this, it will be used in
the original mode as well.

Differential Revision: https://reviews.llvm.org/D115623
2022-03-22 14:04:56 +01:00
Nikita Popov
afb526b3f4 [LICM] Handle store of pointer to itself (PR54495)
Rather than iterating over users and comparing operands, iterate
over uses and check operand number. Otherwise, we'll end up
promoting a store twice if it has two equal operands.

This can only happen with opaque pointers, as otherwise both
operands differ by a level of indirection, so a bitcast would have
to be involved.

Fixes https://github.com/llvm/llvm-project/issues/54495.
2022-03-22 14:00:07 +01:00
Igor Kudrin
c344d97a12 [NVPTX][tests] Do not run tests that require direct object generation
NVPTX does not support generating binary files, which is required for
these tests.

The majority of tests in 'DebugInfo/Generic' also require emitting
object files, so they all are disabled for NVPTX.

Differential Revision: https://reviews.llvm.org/D121996
2022-03-22 16:46:48 +04:00
Igor Kudrin
568404e897 [tests] Make 'object-emission' imply 'default_triple'
If 'config.target_triple' is empty, there is no sense to define the
'object-emission' tag.

Differential Revision: https://reviews.llvm.org/D121994
2022-03-22 16:46:48 +04:00
Igor Kudrin
d7681d9f77 [NVPTX] Avoid a crash when 'llc' is called with '-filetype=null'
For '-filetype=null', 'NVPTXTargetStreamer' is not created, so the
return value of 'OutStreamer->getTargetStreamer()' should be checked
before calling the methods.

Differential Revision: https://reviews.llvm.org/D122001
2022-03-22 16:46:47 +04:00
Igor Kudrin
2881696b40 [tests] Force (some) X86-specific tests to use an explicit triple
These tests are located in 'X86' subfolders which means that they should
be compiled for that target. As they did not have the target specified
explicitly, they in fact were compiled for a default target triple. Not
all targets support all required features for these tests; for example,
if NVPTX is used as a default triple, the tests fail. The patch makes the
tests run for 'x86_64', thus they pass regardless of the default target.

Differential Revision: https://reviews.llvm.org/D121998
2022-03-22 16:46:47 +04:00
Bryan Chan
5269dd7f48 [ThinLTO] Work around buggy FileCheck pattern; NFC
Update the FileCheck patterns in a test case to prevent a path name
containing the `@` character from causing it to fail unnecessarily,
e.g. during a Jenkins CI job.
2022-03-22 08:40:10 -04:00
Sanjay Patel
9e9bda2e8f [InstCombine] try to narrow shifted bswap-of-zext
This is the IR counterpart to 370ebc9d9a573d6
which provided a bswap narrowing fix for issue #53867.

Here we can be more general (although I'm not sure yet
what would happen for illegal types in codegen - too
rare to worry about?):
https://alive2.llvm.org/ce/z/3-CPfo

This will be more effective if we have moved the shift
after the bswap as proposed in D122010, but it is
independent of that patch.

Differential Revision: https://reviews.llvm.org/D122166
2022-03-22 08:22:30 -04:00
Sanjay Patel
c4f31d1da5 [InstCombine] add tests for shift-of-bswap; NFC 2022-03-22 08:22:30 -04:00
David Green
c56dd20f69 [AArch64] Add extra insert subvector cost model tests. NFC 2022-03-22 12:20:19 +00:00
alex-t
7636c9a929 [AMDGPU] use scalar shift for SALU users in frame index elimination
In the frame index lowering we have to insert shift and add
instructions to adjust stack object access.  We need to take care of the stack
object user kind and use scalar shift/add for scalar users.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D121524
2022-03-22 13:16:24 +01:00
Djordje Todorovic
73777b4c35 [Debugify] Optimize debugify original mode
Before we start addressing the issue with having
a lot of false positives when using debugify in
the original mode, we have made a few patches that
should speed up the execution of the testing
utility Passes.

For example, when testing a large project
(let's say LLVM project itself), we can face
a lot of potential DI issues. Usually, we use
-verify-each-debuginfo-preserve (that is very
similar to -debugify-each) -- it collects
DI metadata before each Pass, and after the Pass
it checks if the Pass preserved the DI metadata.
However, we can speed up this process, since we
don't need to collect DI metadata before each
Pass -- we could use the DI metadata that are
collected after the previous Pass from
the pipeline as an input for the next Pass.

This patch speeds up the utility for ~2x.

Differential Revision: https://reviews.llvm.org/D115622
2022-03-22 12:14:00 +01:00
Simon Pilgrim
5a65f0b4d9 [X86][SandyBridge] Remove superfluous mmx store from vector load schedule model group
Noticed by D122216
2022-03-22 10:48:29 +00:00
alex-t
0a488cba2c [AMDGPU] use scalar shift for SALU users in frame index elimination
In the frame index lowering we have to insert shift and add
instructions to adjust stack object access.  We need to take care of the stack
object user kind and use scalar shift/add for scalar users.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D121524
2022-03-22 11:43:23 +01:00
Simon Moll
7de383c892 [VP] Fix VPintrinsic::getStaticVectorLength for vp.merge|select
VPIntrinsic::getStaticVectorLength infers the operational vector length
of a VPIntrinsic instance from a type that is used with the intrinsic.
The function used the mask operand before. Yet, vp.merge|select do not
have a mask operand (in the predicating sense that the other VP
intrinsics are using them - it is a selection mask for them). Fallback
to the return type to fix this.

Reviewed By: kaz7

Differential Revision: https://reviews.llvm.org/D121913
2022-03-22 11:41:23 +01:00
Shengchen Kan
021b42367a [X86] Rename MMX_MOVD64from64rm to MMX_MOVD64from64mr b/c it stores sth, NFC
Reviewed By: pengfei, RKSimon

Differential Revision: https://reviews.llvm.org/D122216
2022-03-22 17:59:28 +08:00