1011 Commits

Author SHA1 Message Date
Samuel Parker
32af267447 [NFC][WebAssembly] Add tests
Add more variations to fpclamptosat.
2023-01-18 13:30:53 +00:00
Nikita Popov
9ed2f14c87 [AsmParser] Remove typed pointer auto-detection
IR is now always parsed in opaque pointer mode, unless
-opaque-pointers=0 is explicitly given. There is no automatic
detection of typed pointers anymore.

The -opaque-pointers=0 option is added to any remaining IR tests
that haven't been migrated yet.

Differential Revision: https://reviews.llvm.org/D141912
2023-01-18 09:58:32 +01:00
Samuel Parker
bba9221d9f [NFC][WebAssembly] Update test
Run update_llc_test_checks.py on address-offsets.ll
2023-01-17 10:34:43 +00:00
Nikita Popov
68a534e9bf [WebAssembly] Convert test to opaque pointers (NFC)
This test was testing both typed and opaque pointers. Remove the
typed pointer check lines, and update the input IR to use opaque
pointers. Note that with opaque pointers, the "bitcast" is not
explicit, but rather just a mismatch in function type between
the call and the declaration.
2023-01-16 10:30:00 +01:00
Nikita Popov
676e22a6df [WebAssembly] Remove redundant opaque pointers test (NFC)
add-prototype.ll has since been converted.
2023-01-16 10:26:11 +01:00
Matt Arsenault
e70ae0f46b DAG/GlobalISel: Fix broken/redundant setting of MODereferenceable
This was incorrectly setting dereferenceable on unaligned
operands. getLoadMemOperandFlags does the alignment dereferenceabilty
check without alignment, and then both paths went on to check
isDereferenceableAndAlignedPointer. Make getLoadMemOperandFlags check
isDereferenceableAndAlignedPointer, and remove the second call.
2023-01-13 20:30:30 -05:00
Luke Lau
275658d1af [SelectionDAG] Implicitly truncate known bits in SPLAT_VECTOR
Now that D139525 fixes the Hexagon infinite loop, the stopgap can be
removed to provide more information about known bits in SPLAT_VECTOR
whose operands are smaller than the bit width (which is most of the
time)

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D141075
2023-01-06 15:43:47 +00:00
Luke Lau
b599a30e93 [WebAssembly][NFC] Add test case for PR59626
For D141079

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D141120
2023-01-06 15:43:44 +00:00
Luke Lau
fb6602616c [WebAssembly] Explicitly add {z,s}ext so extends are selected
During DAG legalization, {u,s}itofp instructions on v2i8, v2i16, v4i8
and v4i16 types ended up being legalized into scalar instructions, when
they could just be extended to v2i32/v4i32 instead.

Fixes https://github.com/llvm/llvm-project/issues/57182

Differential Revision: https://reviews.llvm.org/D140916
2023-01-06 12:28:29 +00:00
Nikita Popov
60442f0d44 [CodeGen] Convert some tests to opaque pointers (NFC)
These are mostly MIR tests, which I did not handle during previous
conversions.
2023-01-05 13:21:20 +01:00
Luke Lau
f841ad30d7 [WebAssembly] Replace LOAD_SPLAT with SPLAT_VECTOR
Splats were selected by matching on uses of `build_vector` with
identical elements, but a while back a target independent node for
vector splatting was added.
This removes the WebAssembly specific LOAD_SPLAT intrinsic, and instead
makes SPLAT_VECTOR legal and adds patterns for splat loads.

Differential Revision: https://reviews.llvm.org/D139871
2023-01-04 15:07:47 +00:00
Luke Lau
2671aa7e84 [WebAssembly][NFC] Add test case for {u,s}itofp on SIMD types
These test cases should be updated in a following patch once fixed
Part of https://github.com/llvm/llvm-project/issues/57182
2023-01-03 19:13:16 +00:00
Nikita Popov
73856247ee [WebAssembly] Convert some tests to opaque pointers (NFC) 2022-12-19 13:07:59 +01:00
Luke Lau
8ef5da7010 [WebAssembly] Fix crash when selecting 64 bit lane extract operand
The tablegen patterns on vector_extract only match i32 constants, but
on wasm64 these come in as i64 constants. In certain situations this
would cause crashes whenever it couldn't select an extract_vector_elt
instruction.
Rather than add duplicate patterns for every instruction, this just
canonicalizes the constant to be i32 when lowering.
Fixes https://github.com/llvm/llvm-project/issues/57577

Differential Revision: https://reviews.llvm.org/D140205
2022-12-19 10:37:19 +00:00
Ron Lieberman
38f1abef86 Revert "[SelectionDAG] Do not second-guess alignment for alloca"
Breaks amdgpu buildbot https://lab.llvm.org/buildbot/#/builders/193
 23491

This reverts commit ffedf47d8b793e07317f82f9c2a5f5425ebb71ad.
2022-12-15 10:55:18 -06:00
Andrew Savonichev
ffedf47d8b [SelectionDAG] Do not second-guess alignment for alloca
Alignment of an alloca in IR can be lower than the preferred alignment
on purpose, but this override essentially treats the preferred
alignment as the minimum alignment.

The patch changes this behavior to always use the specified
alignment. If alignment is not set explicitly in LLVM IR, it is set to
DL.getPrefTypeAlign(Ty) in computeAllocaDefaultAlign.

Tests are changed as well: explicit alignment is increased to match
the preferred alignment if it changes output, or omitted when it is
hard to determine the right value (e.g. for pointers, some structs, or
weird types).

Differential Revision: https://reviews.llvm.org/D135462
2022-12-15 18:18:12 +03:00
Luke Lau
0cd9c51766 [WebAssembly] Use ComplexPattern on remaining memory instructions
This continues the refactoring work of selecting offset + address
operands with the AddrOpsN pattern, previously called LoadOpsN.

This is not an NFC, since constant addresses are now folded into the
offset in more places for v128.storeN_lane.

Differential Revision: https://reviews.llvm.org/D139950
2022-12-15 10:20:06 +00:00
David Green
fd716925ec [DAGCombine] Fold Splat(bitcast(buildvector(x,..))) to splat(x)
This adds a fold which teaches the backend to fold
splat(bitcast(buildvector(x,..))) or
splat(bitcast(scalar_to_vector(x))) to a single splat.

This only handles lane 0 splats, which are only valid under LE, and
needs to be a little careful with the types it creates for the new
buildvector.

Differential Revision: https://reviews.llvm.org/D139611
2022-12-12 08:35:43 +00:00
Paul Robinson
a459529858 [Mips] Convert a test to check 'target=...'
Although it should base the check on host, not target, if possible.

Part of the project to eliminate special handling for triples in lit
expressions.
2022-12-06 15:24:23 -08:00
Samuel Parker
22d87b8212 [NFC][WebAssembly] Add codegen tests 2022-12-05 16:13:05 +00:00
Heejin Ahn
341d4cdeb6 [WebAssembly] Move debug tests into DebugInfo
This moves debug info tests in `test/CodeGen/WebAssembly` into
`test/DebugInfo/WebAssembly`, to gather all wasm debug info related
tests there.

Reviewed By: dschuff

Differential Revision: https://reviews.llvm.org/D138871
2022-11-29 11:13:42 -08:00
Paulo Matos
bab98395a1 [WebAssembly] Remove unnecessary GEP insts from table tests
Removes the unnecessary GEP instructions from WebAssembly Table tests.

Differential Revision: https://reviews.llvm.org/D138569
2022-11-23 18:45:52 +01:00
Simon Pilgrim
629f17c516 [DAG] isGuaranteedNotToBeUndefOrPoison - handle FrameIndex/TargetFrameIndex
Fixes #58904
2022-11-22 18:16:15 +00:00
Heejin Ahn
d9ae0788c4 [WebAssembly] Disable register coalescing at -O1
This disables `RegisterCoalescer` pass at -O1, which currently runs for
all levels except for -O0, as a part of common optimization pipeline.

`RegisterCoalescer` pass degrades Wasm debug info quality by a
significant margin. When I use `LiveDebugValue` analysis, disabling this
increases the average PC ranges covered by 15% on Emscripten core
benchmarks (52% -> 66.8%). (Our code is currently not using
`LiveDebugValues` analysis at the moment, and the experiment was done on
a local setting that enabled it. I'm planning to upstream it soon.)

In Emscripten core benchmarks, disabling this at -O1 causes +4.5% in
code size and +1% in the number of locals. The number of globals stays
the same. I believe this tradeoff is acceptable given that -O1 is not
usually used in production builds and is often used for debugging when
the application size is very large.

The plan is to investigate and fix what's causing the degradation in
that pass, but for now disabling it seems like a low-hanging quick fix.

Reviewed By: dschuff

Differential Revision: https://reviews.llvm.org/D138455
2022-11-21 14:16:04 -08:00
Thomas Lively
ae96b5bd2d [WebAssembly] Update relaxed-simd instruction names
Including builtin and intrinsic names. These should be the final names for the
proposal.
https://github.com/WebAssembly/relaxed-simd/blob/main/proposals/relaxed-simd/Overview.md

Reviewed By: aheejin, maratyszcza

Differential Revision: https://reviews.llvm.org/D138249
2022-11-21 12:40:15 -08:00
Samuel Parker
b303c0027f [WebAssembly] multivalue stackify fix
Don't attempt to move a multivalue def past one of it's prior uses.

Differential Revision: https://reviews.llvm.org/D137824
2022-11-16 09:02:40 +00:00
Nikita Popov
d35fcf0e97 [WebAssembly] Use default attributes for intrinsics
This switches wasm intrinsics to use default attributes,
i.e. nofree, nosync, nocallback and willreturn. Especially
willreturn will be required to avoid optimization regressions
in the future.

The attributes are omitted from the trapping fptoi intrinsics
(where I assume trapping is considered well-defined, and as such
these aren't willreturn), the throw/rethrow intrinsics (which
will unwind) and the atomic intrinsics (which aren't nosync).

Differential Revision: https://reviews.llvm.org/D137551
2022-11-07 17:05:36 +01:00
Dan Gohman
0807bc7e07 [wasm-ld] Update supported features in the generic CPU configuration
Accompanying https://reviews.llvm.org/D125728, this updates LLVM
Codegen's "generic" CPU to enable the same new features.

Differential Revision: https://reviews.llvm.org/D125729
2022-11-02 12:51:28 -07:00
Douglas Yung
fc40c73921 Revert "Update supported features in the generic CPU configuration"
This reverts commit 11afbf396e10e1b1e91a5991e2aec1916e29a910.

There are 10 tests still failing after follow-up fix b5d0bf9b9853, this should get the following bots back to green:
 - https://lab.llvm.org/buildbot/#/builders/183/builds/8194
 - https://lab.llvm.org/buildbot/#/builders/186/builds/9491
 - https://lab.llvm.org/buildbot/#/builders/214/builds/3908
 - https://lab.llvm.org/buildbot/#/builders/93/builds/11740
 - https://lab.llvm.org/buildbot/#/builders/231/builds/4200
 - https://lab.llvm.org/buildbot/#/builders/121/builds/24519
 - https://lab.llvm.org/buildbot/#/builders/230/builds/4466
 - https://lab.llvm.org/buildbot/#/builders/94/builds/11639
 - https://lab.llvm.org/buildbot/#/builders/45/builds/9325
 - https://lab.llvm.org/buildbot/#/builders/124/builds/5219
 - https://lab.llvm.org/buildbot/#/builders/67/builds/8623
 - https://lab.llvm.org/buildbot/#/builders/123/builds/13836
 - https://lab.llvm.org/buildbot/#/builders/109/builds/49355
 - https://lab.llvm.org/buildbot/#/builders/58/builds/27751
 - https://lab.llvm.org/buildbot/#/builders/117/builds/9922
 - https://lab.llvm.org/buildbot/#/builders/16/builds/37012
 - https://lab.llvm.org/buildbot/#/builders/104/builds/9490
 - https://lab.llvm.org/buildbot/#/builders/42/builds/7725
 - https://lab.llvm.org/buildbot/#/builders/196/builds/20077
 - https://lab.llvm.org/buildbot/#/builders/3/builds/15217
 - https://lab.llvm.org/buildbot/#/builders/6/builds/15251
 - https://lab.llvm.org/buildbot/#/builders/9/builds/15247
 - https://lab.llvm.org/buildbot/#/builders/36/builds/26487
 - https://lab.llvm.org/buildbot/#/builders/54/builds/2474
 - https://lab.llvm.org/buildbot/#/builders/74/builds/14536
 - https://lab.llvm.org/buildbot/#/builders/5/builds/28555
2022-10-25 16:34:08 -07:00
Dan Gohman
11afbf396e Update supported features in the generic CPU configuration
Accompanying https://reviews.llvm.org/D125728, this updates LLVM
Codegen's "generic" CPU to enable the same new features.

Differential Revision: https://reviews.llvm.org/D125729
2022-10-25 11:42:32 -07:00
Peter Rong
c2e7c9cb33 [CodeGen] Using ZExt for extractelement indices.
In https://github.com/llvm/llvm-project/issues/57452, we found that IRTranslator is translating `i1 true` into `i32 -1`.
This is because IRTranslator uses SExt for indices.

In this fix, we change the expected behavior of extractelement's index, moving from SExt to ZExt.
This change includes both documentation, SelectionDAG and IRTranslator.
We also included a test for AMDGPU, updated tests for AArch64, Mips, PowerPC, RISCV, VE, WebAssembly and X86

This patch fixes issue #57452.

Differential Revision: https://reviews.llvm.org/D132978
2022-10-15 15:45:35 -07:00
Sam Clegg
664a5c6d03 [WebAssembly] Fix return type of __builtin_return_address under wasm64
Differential Revision: https://reviews.llvm.org/D135005
2022-10-03 08:31:52 -07:00
Paulo Matos
1bd1a44070 [WebAssembly] Use intrinsics for table.get/set instructions
Initial table.get/set implementation would match and lower combinations
of GEP+load/store to table.get/set instructions. However, this is error
prone due to potential combinations of GEP+load/store we don't implement,
and load/store optimizations. By changing the code to using intrinsics, we
 avoid both issues and simplify the code.

New builtins implemented:
* @llvm.wasm.table.get.externref
* @llvm.wasm.table.get.funcref
* @llvm.wasm.table.set.externref
* @llvm.wasm.table.set.funcref

Reviewed By: asb, tlively

Differential Revision: https://reviews.llvm.org/D134436
2022-09-27 09:16:30 +02:00
Fanchen Kong
8a2729fea7 [WebAssembly] Improve codegen for loading scalars from memory to v128
Use load32_zero instead of load32_splat to load the low 32 bits from memory to
v128. Test cases are added to cover this change.

Reviewed By: tlively

Differential Revision: https://reviews.llvm.org/D134257
2022-09-21 21:05:44 -07:00
Fanchen Kong
28557e8c98 [WebAssembly] Improve codegen for shuffles with undefined lane indices
For undefined lane indices, fill the mask with {0..N} instead of zeros to allow
further reduction to word/dword shuffle on the VM.

Reviewed By: tlively, penzn

Differential Revision: https://reviews.llvm.org/D133473
2022-09-13 16:03:18 -07:00
Thomas Lively
ac3b8df8f2 [WebAssembly] Prototype f32x4.relaxed_dot_bf16x8_add_f32
As proposed in https://github.com/WebAssembly/relaxed-simd/issues/77. Only an
LLVM intrinsic and a clang builtin are implemented. Since there is no bfloat16
type, use u16 to represent the bfloats in the builtin function arguments.

Differential Revision: https://reviews.llvm.org/D133428
2022-09-08 08:07:49 -07:00
Sam Clegg
349a2c37f9 [WebAssembly][MC] Update tests after recent removal of .size directives for functions
These were missing from https://reviews.llvm.org/D132929
2022-08-31 14:54:13 -07:00
Stephen Long
525af9f8eb [MC] Omit fill value if it's zero when emitting code alignment
Previously, we were generating zeroes when generating code alignments for AArch64, but now we should omit the value and let the assembler choose to generate nops or zeroes.

Reviewed By: efriedma, MaskRay

Differential Revision: https://reviews.llvm.org/D132508
2022-08-25 10:07:33 -07:00
Sam Clegg
fa306f1396 [WebAssembly] WebAssemblyLowerEmscriptenEHSjLj: Fix signature of malloc in wasm64 mode
Differential Revision: https://reviews.llvm.org/D132091
2022-08-17 18:16:34 -07:00
Alex Bradbury
104a24ec8b [WebAssembly] Produce error when encountering unlowerable Wasm global accesses
WebAssembly globals are represented as IR globals with the wasm_var
address space (AS1). Prior to this patch, a wasm global load that isn't
lowerable will produce a failure to select, while a wasm global store
will produced incorrect code. This patch ensures we consistently produce
a clear error.

As noted in the test cases, it's conceivable that a frontend or an
optimisation pass could produce similar IR even in the presence of the
semantic restrictions on pointers to Wasm globals in the frontend, which
is a separate problem to address.

Differential Revision: https://reviews.llvm.org/D131387
2022-08-10 10:34:10 +01:00
Thomas Lively
b19de814ad [WebAssembly] Improve codegen for v128.bitselect
Add patterns selecting ((v1 ^ v2) & c) ^ v2 and ((v1 ^ v2) & ~c) ^ v2 to
v128.bitselect.

Resolves #56827.

Reviewed By: aheejin

Differential Revision: https://reviews.llvm.org/D131131
2022-08-03 23:28:37 -07:00
Nuno Lopes
fffabd5348 [NFC] Switch a few uses of undef to poison as placeholders for unreachable code 2022-07-30 13:55:56 +01:00
Andrew Brown
3696a789d2 [WebAssembly] Use localexec as default TLS model for non-Emscripten targets
Only Emscripten supports dynamic linking with threads. To use
thread-local storage for other targets, this change defaults to the
`localexec` model.

Differential Revision: https://reviews.llvm.org/D130053
2022-07-25 13:25:46 -07:00
Fangrui Song
5e6936e5bc [test] Change -lowertypetests tests to -passes= 2022-07-17 15:03:46 -07:00
chenglin.bi
8c74205642 [SelectionDAG][DAGCombiner] Reuse exist node by reassociate
When already have (op N0, N2), reassociate (op (op N0, N1), N2) to (op (op N0, N2), N1) to reuse the exist (op N0, N2)

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D122539
2022-06-24 23:15:06 +08:00
Alex Bradbury
80fb782336 [WebAssembly][NFC] Update reftype and table tests to use opaque pointers
Differential Revision: https://reviews.llvm.org/D126535
2022-06-20 10:57:41 +01:00
Thomas Lively
aff679a48c [WebAssembly] Implement remaining relaxed SIMD instructions
Add codegen, intrinsics, and builtins for the i16x8.relaxed_q15mulr_s,
i16x8.dot_i8x16_i7x16_s, and i32x4.dot_i8x16_i7x16_add_s instructions. These are
the last instructions from the relaxed SIMD proposal[1] that had not been
implemented.

[1]:
https://github.com/WebAssembly/relaxed-simd/blob/main/proposals/relaxed-simd/Overview.md.

Differential Revision: https://reviews.llvm.org/D127170
2022-06-08 10:32:10 -07:00
Simon Pilgrim
26053cddb4 [WebAssembly] Regenerate simd-build-vector.ll to show full codegen 2022-06-08 16:54:26 +01:00
Serguei Katkov
24e16e4af2 [SSAUpdaterImpl] Do not generate phi node with all the same incoming values
If all available vals to basic block are the same - do not build new phi node and
just use this value.

Reviewed By: sameerds
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D126525
2022-06-03 12:24:33 +07:00
Nuno Lopes
80b3dcc045 [Support] Make report_fatal_error respect its GenCrashDiag argument so it doesn't generate a backtrace
There are a few places where we use report_fatal_error when the input is broken.
Currently, this function always crashes LLVM with an abort signal, which
then triggers the backtrace printing code.
I think this is excessive, as wrong input shouldn't give a link to
LLVM's github issue URL and tell users to file a bug report.
We shouldn't print a stack trace either.

This patch changes report_fatal_error so it uses exit() rather than
abort() when its argument GenCrashDiag=false.

Reviewed by: nikic, MaskRay, RKSimon

Differential Revision: https://reviews.llvm.org/D126550
2022-05-30 19:19:23 +01:00