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88 Commits

Author SHA1 Message Date
Akira Hatanaka
049e9e4d22 This patch makes the following changes necessary for MIPS' direct code emission. 
- lower unaligned loads/stores.
- encode the size operand of instructions INS and EXT.
- emit relocation information needed for JAL (jump-and-link).  

llvm-svn: 145113
 2011-11-23 22:19:28 +00:00
Akira Hatanaka
1c0590c5da Remove MipsMCSymbolRefExpr. 
llvm-svn: 144654
 2011-11-15 18:20:08 +00:00
Bruno Cardoso Lopes
c85e3ff334 Mips MC object code emission improvements: 
"With this patch we can now generate runnable Mips code through LLVM
direct object emission. We have run numerous simple programs, both C
and C++ and with -O0 and -O3 from the output. The code is not production
ready, but quite useful for experimentation." Patch and message by
Jack Carter

llvm-svn: 144414
 2011-11-11 22:58:42 +00:00
Bruno Cardoso Lopes
d5edb3847a Properly handle Mips MC relocations and lower cpload and cprestore macros to MCInsts. 
Patch by Jack Carter.

llvm-svn: 144139
 2011-11-08 22:26:47 +00:00
Benjamin Kramer
20baffb257 Replace (Lower|Upper)caseString in favor of StringRef's newest methods. 
llvm-svn: 143891
 2011-11-06 20:37:06 +00:00
Akira Hatanaka
1c18465859 Fix function isUnalignedLoadStore. 
llvm-svn: 141722
 2011-10-11 22:04:01 +00:00
Akira Hatanaka
557c8e3443 Add patterns for unaligned load and store instructions and enable the 
instruction selector to generate them.

llvm-svn: 141471
 2011-10-08 02:24:10 +00:00
Akira Hatanaka
25ce3647e5 Add enums and functions for symbols Mips64 uses. 
llvm-svn: 140295
 2011-09-22 03:09:07 +00:00
Akira Hatanaka
3d673cc323 Add a base class for Mips TargetMachines and add Mips64 TargetMachines. 
llvm-svn: 140233
 2011-09-21 03:00:58 +00:00
Akira Hatanaka
8b983d9773 O64 will not be supported. 
llvm-svn: 139421
 2011-09-09 22:22:48 +00:00
Akira Hatanaka
4444daeec5 Drop support for Mips1 and Mips2. 
llvm-svn: 139405
 2011-09-09 20:45:50 +00:00
Evan Cheng
2bb4035707 Move TargetRegistry and TargetSelect from Target to Support where they belong. 
These are strictly utilities for registering targets and components.

llvm-svn: 138450
 2011-08-24 18:08:43 +00:00
Akira Hatanaka
b2e7558c40 Add support for half-word unaligned loads and stores. 
llvm-svn: 137848
 2011-08-17 18:49:18 +00:00
Akira Hatanaka
2263c10946 Fix handling of double precision loads and stores when Mips1 is targeted. 
Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This 
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.

Without the changes made in this patch, llc produces code that has the same 
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.

llvm-svn: 137711
 2011-08-16 03:51:51 +00:00
Akira Hatanaka
2fcc1cfdce Define unaligned load and store. 
llvm-svn: 137515
 2011-08-12 21:30:06 +00:00
Evan Cheng
61faa55b74 Separate MCInstPrinter registration from AsmPrinter registration. 
llvm-svn: 135974
 2011-07-25 21:20:24 +00:00
Akira Hatanaka
9c6028f98e Lower MachineInstr to MC Inst and print to .s files. 
llvm-svn: 134661
 2011-07-07 23:56:50 +00:00
Akira Hatanaka
9f6f6f6ecc Rather than having printMemOperand change the way memory operands are printed 
based on a modifier, split it into two functions.

llvm-svn: 134637
 2011-07-07 20:54:20 +00:00
Akira Hatanaka
ddd1265316 Change visibility of MipsAsmPrinter. 
llvm-svn: 134630
 2011-07-07 20:10:52 +00:00
Akira Hatanaka
2e766ed2f8 Reverse order of operands of address operand mem so that the base operand comes 
before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.

llvm-svn: 134625
 2011-07-07 18:57:00 +00:00
Akira Hatanaka
ac4db9251b Add missing return statement. 
llvm-svn: 134622
 2011-07-07 18:27:36 +00:00
Akira Hatanaka
f2bcad972d Improve Mips back-end's handling of DBG_VALUE. 
llvm-svn: 134224
 2011-07-01 01:04:43 +00:00
Akira Hatanaka
4c406e7457 Re-apply 132758 and 132768 which were speculatively reverted in 132777. 
llvm-svn: 133494
 2011-06-21 00:40:49 +00:00
Eric Christopher
f15601f19a Speculatively revert 132758 and 132768 to try to fix the Windows buildbots. 
llvm-svn: 132777
 2011-06-09 16:03:19 +00:00
Akira Hatanaka
0683a7212e Initial support for inline asm memory operand constraints. 
llvm-svn: 132768
 2011-06-09 03:31:05 +00:00
Bruno Cardoso Lopes
bf3c1251e0 This patch implements the thread local storage. Implemented are General 
Dynamic, Initial Exec and Local Exec TLS models.

Patch by Sasa Stankovic

llvm-svn: 132322
 2011-05-31 02:53:58 +00:00
Akira Hatanaka
2db176c4c1 Enable printing of immediates that do not fit in 16-bit. .cprestore can have 
offsets that are larger than 0x10000.

llvm-svn: 132003
 2011-05-24 21:22:21 +00:00
Akira Hatanaka
90d96f44ce Fix MipsAsmPrinter::printSavedRegsBitmaskChange. Remove functions and variables 
in MipsFunctionInfo that are no longer used.

llvm-svn: 131917
 2011-05-23 20:34:30 +00:00
Akira Hatanaka
e24891251c Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. 
llvm-svn: 129612
 2011-04-15 21:51:11 +00:00
Akira Hatanaka
aef55c8801 Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality. 
llvm-svn: 129606
 2011-04-15 21:00:26 +00:00
Akira Hatanaka
977f555a76 Insert space before ';' to prevent warnings. 
llvm-svn: 128750
 2011-04-02 00:15:58 +00:00
Akira Hatanaka
56d9ef53a2 Simplifies logic for printing target flags. 
llvm-svn: 128741
 2011-04-01 21:41:06 +00:00
Akira Hatanaka
e625ba46b7 Modifies MipsAsmPrinter::isBlockOnlyReachableByFallthrough so that it handles delay slots correctly. 
llvm-svn: 128724
 2011-04-01 18:57:38 +00:00
Bruno Cardoso Lopes
f8198e4311 Lowers block address. Currently asserts when relocation model is not PIC. Patch by Akira Hatanaka 
llvm-svn: 127027
 2011-03-04 20:01:52 +00:00
Bruno Cardoso Lopes
ed874eff93 Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira 
llvm-svn: 127003
 2011-03-04 17:51:39 +00:00
Anton Korobeynikov
2f93128109 Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there. 
llvm-svn: 123170
 2011-01-10 12:39:04 +00:00
Bruno Cardoso Lopes
f0c6e3780d Match a pattern generated by a dag combiner opt where: 
(select (load (load tga0)) (load tga1)) => (load (select (load tga0) tga1))

Thanks to Akira for pointing that.

llvm-svn: 121163
 2010-12-07 19:00:20 +00:00
Anton Korobeynikov
0eecf5d201 Move hasFP() and few related hooks to TargetFrameInfo. 
llvm-svn: 119740
 2010-11-18 21:19:35 +00:00
Chris Lattner
66031ed839 move all the target's asmprinters into the main target. The piece 
that should be split out is the InstPrinter (if a target is mc'ized).
This change makes all the targets be consistent.

llvm-svn: 119056
 2010-11-14 18:43:56 +00:00
Anton Korobeynikov
06d2d8ba72 Separate MIPS asmprinter 
llvm-svn: 68383
 2009-04-03 10:41:41 +00:00
Evan Cheng
5e5a63cf8f CodeGen still defaults to non-verbose asm, but llc now overrides it and default to verbose. 
llvm-svn: 67668
 2009-03-25 01:47:28 +00:00
Duncan Sands
4581bebf2a It makes no sense to have a ODR version of common 
linkage, so remove it.

llvm-svn: 66690
 2009-03-11 20:14:15 +00:00
Duncan Sands
12da8ce3d2 Introduce new linkage types linkonce_odr, weak_odr, common_odr 
and extern_weak_odr.  These are the same as the non-odr versions,
except that they indicate that the global will only be overridden
by an *equivalent* global.  In C, a function with weak linkage can
be overridden by a function which behaves completely differently.
This means that IP passes have to skip weak functions, since any
deductions made from the function definition might be wrong, since
the definition could be replaced by something completely different
at link time.   This is not allowed in C++, thanks to the ODR
(One-Definition-Rule): if a function is replaced by another at
link-time, then the new function must be the same as the original
function.  If a language knows that a function or other global can
only be overridden by an equivalent global, it can give it the
weak_odr linkage type, and the optimizers will understand that it
is alright to make deductions based on the function body.  The
code generators on the other hand map weak and weak_odr linkage
to the same thing.

llvm-svn: 66339
 2009-03-07 15:45:40 +00:00
Bill Wendling
c5437ea429 Overhaul my earlier submission due to feedback. It's a large patch, but most of 
them are generic changes.

- Use the "fast" flag that's already being passed into the asm printers instead
  of shoving it into the DwarfWriter.

- Instead of calling "MI->getParent()->getParent()" for every MI, set the
  machine function when calling "runOnMachineFunction" in the asm printers.

llvm-svn: 65379
 2009-02-24 08:30:20 +00:00
Bill Wendling
0f4c581c4a Put code that generates debug labels into TableGen so that it can be used by 
everyone.

llvm-svn: 64978
 2009-02-18 23:12:06 +00:00
Rafael Espindola
6de96a1b5d Add the private linkage. 
llvm-svn: 62279
 2009-01-15 20:18:42 +00:00
Duncan Sands
dc020f9c3c Rename getABITypeSize to getTypePaddedSize, as 
suggested by Chris.

llvm-svn: 62099
 2009-01-12 20:38:59 +00:00
Dan Gohman
0d1e9a8e04 Switch the MachineOperand accessors back to the short names like 
isReg, etc., from isRegister, etc.

llvm-svn: 57006
 2008-10-03 15:45:36 +00:00
Duncan Sands
08d91178e9 Rename isWeakForLinker to mayBeOverridden. Use it 
instead of hasWeakLinkage in a bunch of optimization
passes.

llvm-svn: 56782
 2008-09-29 11:25:42 +00:00
Anton Korobeynikov
076e905b94 Move actual section printing stuff to AsmPrinter from TAI reducing heap traffic. 
llvm-svn: 56573
 2008-09-24 22:14:23 +00:00