6474 Commits

Author SHA1 Message Date
Nelson Chu
0b9a620b83 [RISCV] Support assembler and dis-assembler for VCIX extension.
Spec: https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf

Differential Revision: https://reviews.llvm.org/D144530
2023-04-09 20:41:01 -07:00
Andrew Ng
a3aa916d01 [Support] Improve Windows performance of buffered raw_ostream
The "preferred" buffer size for raw_ostream is set to BUFSIZ which on
Windows is only 512. This results in more calls to write and this
overhead can have a significant negative impact on performance,
especially when Anti-Virus is also involved.

Therefore increase the "preferred" buffer size to 16KB for Windows.

One example of where this helps is the LLD --Map option which dumps out
the symbol map for a link. In a link of UE4, this change has been seen
to improve the performance of the symbol map writing by more than a
factor of 6.

Differential Revision: https://reviews.llvm.org/D147340
2023-04-05 11:03:12 +01:00
David Majnemer
3d11652bbe [APFloat] Refactor common code for APFloat<->APInt conversion
All the IEEE formats are quite similar, we can merge their code
effectively by writing it parametrically via the fltSemantics object.

We can metaprogram the implementation such that this parametricity is
zero-cost.
2023-04-04 19:12:10 +00:00
Craig Topper
dc90af501f [RISCV] Bump I, F, D, and A extension versions to 20191214 spec version
New versions I2.1, F2.2, D2.2 A2.1

Make F and Zfinx imply Zicsr.
Make G imply Zifencei.

This should have no impact to generated code. We have no plans to require Zicsr/Zifencei extension to be explicitly enabled to use Zicsr/Zifencei instructions in assembly.

See https://reviews.llvm.org/D147183 for documentation regarding what version specification we implement.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D147179
2023-03-30 15:28:44 -07:00
Craig Topper
8c124e3c41 [RISCV] isDigit instead of isdigit for consistency. NFC
There are several other calls to isDigit in RISCVISAInfo.cpp
2023-03-30 00:11:12 -07:00
Craig Topper
24bc5f3f31 [RISCV] Replace std::string with StringRef in RISCVISAInfo. NFC
We're just slicing off part of an existing StringRef. No need to
allocate any new storage.
2023-03-29 22:24:08 -07:00
Craig Topper
e2630a5b4c [RISCV] Use StringRef(&C, 1) instead of std::string(1, C).
We're calling functions that take a StringRef. We can create one
from a single character variable without using std::string.
2023-03-29 21:51:24 -07:00
Alex Bradbury
d3291c692c [RISCV][MC] Add support for the experimental zicond extension
This patch adds the basic MC layer support for Zicond, based on
[1.0-rc1](https://github.com/riscv/riscv-zicond/releases/tag/v1.0-rc1).
As with other extensions, if there are additional changes between
release candidates without incrementing the version number we won't be
able to reflect that in the version number. I believe we've previously
decided this is not a problem for extensions still considered
experimental (i.e. not yet ratified).

Differential Revision: https://reviews.llvm.org/D146946
2023-03-29 12:17:50 +01:00
Craig Topper
29463612d2 [RISCV] Replace RISCV -> RISC-V in comments. NFC
To be consistent with RISC-V branding guidelines
https://riscv.org/about/risc-v-branding-guidelines/
Think we should be using RISC-V where possible.

More patches will follow.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D146449
2023-03-27 09:50:17 -07:00
Priyanshi Agarwal
4071dcf354 [documentation] Fix Typos
Fixes https://github.com/llvm/llvm-project/issues/56747

Patch By: ipriyanshi1708

Differential Revision: https://reviews.llvm.org/D146644
2023-03-27 10:20:08 +01:00
Alex Bradbury
062065888f [RISCV] Enable tools such as llvm-objdump to process objects with unrecognised base ISA versions
Tools such as llvm-objdump will currently inputs when the base ISA has
an unrecognised version. I addressed a similar issue in LLD in D144353,
introducing parseArchStringNormalized. While it would make sense to
migrate `llvm/lib/Object/ELFObjectFile.cpp` to using
`parseArchStringNormalized` as well, this patch takes a less ambitious
initial step. By tweaking the behaviour of `parseArchString` when
`IgnoreUnknown` is true (which only has one in-tree user), we use the
default supported ISA version when a base ISA with unrecognised version
is encountered.

This means that llvm-objdump and related tools will function better for
objects produced from a recent GCC. This isn't a full fix, as
IgnoreUnknown means that an imafd object with attributes specifying
newer A/F/D versions will have those extensions ignored.

Differential Revision: https://reviews.llvm.org/D146070
2023-03-27 04:32:58 +01:00
Alex Bradbury
af602edf0e [RISCV] Make RISCVISAInfo::toFeatureVector ignore unsupported extensions
parseNormalizedArchString adds a code path that creates a RISCVISAInfo
including extensions that may not be supported by LLVM (rather than
erroring or just ignoring them). Therefore, toFeatureVector needs to
check the extension is supported in order to avoid creating unrecognised
feature strings.

This change shouldn't impact any code paths used outside of test code,
but this will be relied upon by the next patch which moves llvm-objdump
and related tools over to using parseNormalizedArchString.

Differential Revision: https://reviews.llvm.org/D146113
2023-03-26 15:51:38 +01:00
4vtomat
9795aa042a [RISCV] Support vector crypto extension ISA string and assembly
LLVM implements the 0.3 draft specification:
https://github.com/riscv/riscv-crypto/releases/download/v20230206/riscv-crypto-spec-vector.pdf
, and current vector crypto extension version can be found in:
https://github.com/riscv/riscv-crypto.

Differential Revision: https://reviews.llvm.org/D141672
2023-03-25 05:15:55 -07:00
David Majnemer
2f086f265b [APFloat] Add E4M3B11FNUZ
X. Sun et al. (https://dl.acm.org/doi/10.5555/3454287.3454728) published
a paper showing that an FP format with 4 bits of exponent, 3 bits of
significand and an exponent bias of 11 would work quite well for ML
applications.

Google hardware supports a variant of this format where 0x80 is used to
represent NaN, as in the Float8E4M3FNUZ format. Just like the
Float8E4M3FNUZ format, this format does not support -0 and values which
would map to it will become +0.

This format is proposed for inclusion in OpenXLA's StableHLO dialect: https://github.com/openxla/stablehlo/pull/1308

As part of inclusion in that dialect, APFloat needs to know how to
handle this format.

Differential Revision: https://reviews.llvm.org/D146441
2023-03-24 20:06:40 +00:00
Job Noorman
c39dd7c1db [RISCV][MC] Add support for RV64E
Implement MC support for the recently ratified RV64E base instruction
set.

Differential Revision: https://reviews.llvm.org/D143570
2023-03-23 12:32:25 +00:00
Job Noorman
d25751779b Bump RV32E version to 2.0
RV32E was recently [ratified](afd613691c) so we should update the version as our MC-layer support is complete.

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D144384
2023-03-23 18:12:26 +08:00
Craig Topper
37f3e53c5b [RISCV] Simplify RISCVISAInfo::compareExtension. NFCI
Instead of having a separate single letter and multiletter ranking
use a unified rank that assigns multiletter a larger value than
single letter.

Once we've ranked the extensions, then we compare using these ranks.

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D146273
2023-03-20 22:25:11 -07:00
Craig Topper
91b3051ac8 [RISCV] Remove ExtName from RISCVExtensionInfo.
This field is never used in the compiler and was only used in
unit tests added recently.

It's only used as the value in a map where the extension name
is the key. If we need the string we can get it from the key.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D146197
2023-03-16 15:20:25 -07:00
Kazu Hirata
8bdf387858 Use *{Map,Set}::contains (NFC)
Differential Revision: https://reviews.llvm.org/D146104
2023-03-15 08:46:32 -07:00
Kazu Hirata
b595eb83e5 [llvm] Use *{Set,Map}::contains (NFC) 2023-03-14 18:56:07 -07:00
Alex Bradbury
cb743dd837 [RISCV] Consistently error for arch strings with trailing _
RISCVISAInfo::parseArchString would sometimes error for arch strings
with a trailing _ and sometimes accept them. This patch makes it
consistently error.

Differential Revision: https://reviews.llvm.org/D145949
2023-03-14 19:12:07 +00:00
Alex Bradbury
b2fad8027a [RISCV][NFC] Small refactor in RISCVISAInfo::parseArchString
Slightly refactor handling of version extraction for the 'baseline' ISA,
to make an upcoming patch easier to review.
2023-03-14 16:37:34 +00:00
Alex Bradbury
e9a03f360f [RISCV] Reject 'g' with explicit version in parseArchString
There is no versioning scheme for the 'g' shorthand for imafd (or in
current ISA specs, imafd_zifencei_zicsr). As such, the only sensible
behaviour to me seems to be to reject a version for it.

Differential Revision: https://reviews.llvm.org/D145954
2023-03-14 12:46:13 +00:00
Kadir Cetinkaya
710983ab54
[Support][MemBuffer] Prevent UB on empty StringRefs
Empty StringRefs are usually identified by their length being zero, and
sometimes they'll have Data==nullptr (e.g. default constructed, or derived from
an operation like split/copy and result turned out to be empty).

If such StringRef objects are passed to llvm::MemoryBuffer::getMemBufferCopy,
it'll result in UB as neither src nor dst can be null, even if size is zero.

This patch prevents that UB by not issuing a copy whenever StringRef is empty.

Differential Revision: https://reviews.llvm.org/D144706
2023-03-14 12:58:37 +01:00
Alex Bradbury
a159e58c00 Reland [RISCV] Fix gaps in IgnoreUnknown=true for RISCVISAInfo::parseArchString
Prior to this patch, unrecognised z/s/sx/x prefixed extensions were not
ignored when IgnoreUnknown=true.

The first version of this patch, a7313f83b9ca9, incorrectly used
`!isSupportedExtension(Ext)` rather than `!isSupportedExtension(Name)`.
i.e. checked the full substring rather than the split out name, causing
incorrect behaviour when a version is specified. This was fixed and a
new test case addded.

Differential Revision: https://reviews.llvm.org/D145882
2023-03-13 15:19:15 +00:00
Alex Bradbury
7054aa6d6d Revert "[RISCV] Fix gaps in IgnoreUnknown=true for RISCVISAInfo::parseArchString"
This reverts commit a7313f83b9ca904fade446e000550c69e0887cbf.

Causes a buildbot failure.
2023-03-13 11:20:28 +00:00
Alex Bradbury
a7313f83b9 [RISCV] Fix gaps in IgnoreUnknown=true for RISCVISAInfo::parseArchString
Prior to this patch, unrecognised z/s/sx/x prefixed extensions were not
ignored when IgnoreUnknown=true.

Differential Revision: https://reviews.llvm.org/D145882
2023-03-13 10:53:05 +00:00
Craig Topper
de76c016f7 [RISCV] Consistently place single quotes around extension names in error messages.
Some extensions had them, some did not.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D145817
2023-03-10 12:36:37 -08:00
Craig Topper
2800d57e12 [RISCV] Error if F and Zfinx extensions are specified together.
Fixes #61277

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D145809
2023-03-10 11:26:00 -08:00
Craig Topper
90f6a4cc73 [RISCV] Make D extension imply F extension.
I believe this implies relationship is documented in the current
spec but may have been less clear in an older spec.

We used to report an error so I think it should be ok to change this.
Only someone expecting the error should be impacted.

Reviewed By: asb, luismarques

Differential Revision: https://reviews.llvm.org/D145125
2023-03-06 19:59:47 -08:00
Luís Marques
c111fe46a1 [Support] Implement findModulesAndOffsets on Apple 64-bit platforms
To have line number information in stack traces (per stack frame) it's
necessary to implement findModulesAndOffsets.

Differential Revision: https://reviews.llvm.org/D142282
2023-03-05 12:20:47 +00:00
Matt Arsenault
71f1ea2c15 APFloat: Add classify 2023-03-03 18:54:58 -04:00
Matt Arsenault
18fa83ed36 ADT: Move some FPClassTest utility functions out of instcombine 2023-03-03 18:20:47 -04:00
Matt Arsenault
0eb59cab95 ADT: Move FPClassTest printing functions to common place 2023-03-03 18:20:47 -04:00
Luís Marques
6190356914 Revert "[Support] Implement findModulesAndOffsets on Apple 64-bit platforms"
This reverts commit b8b8aa6f06458212193c4202291c9f68364b2025.
It broke AIX.
2023-03-02 21:44:34 +00:00
Sander de Smalen
170e7a0ec2 [AArch64][SME2] Add CodeGen support for target("aarch64.svcount").
This patch adds AArch64 CodeGen support such that the type can be passed
and returned to/from functions, and also adds support to use this type in
load/store operations and PHI nodes.

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D136862
2023-03-02 12:07:41 +00:00
Luís Marques
b8b8aa6f06 [Support] Implement findModulesAndOffsets on Apple 64-bit platforms
To have line number information in stack traces (per stack frame) it's
necessary to implement findModulesAndOffsets.

Differential Revision: https://reviews.llvm.org/D142282
2023-03-02 10:58:56 +00:00
Alex Bradbury
ff93c9beef [lld][RISCV] Avoid error when encountering unrecognised ISA extensions/versions in RISC-V attributes
This patch follows on from this RFC thread
<https://discourse.llvm.org/t/rfc-resolving-issues-related-to-extension-versioning-in-risc-v/68472/>
and the ensuing discussion in the RISC-V LLVM sync-up call. The
consensus agreed that the behaviour change in LLD introduced in D138550
that results in object files including arch attributes with unrecognised
extensions or versions of extensions is a regression and should be
treated as such. As it stands, this logic means that LLD will error out
if trying to link a RISC-V object file from LLVM HEAD (rv32i2p0/rv64i2p0)
with one from current GCC (rv32i2p1/rv64i2p1 by default).

There's a bigger discussion about exactly when to warn vs error and so
on, and how to control that, and this patch doesn't attempt to address
all those questions. It simply tries to fix the problem with a minimally
invasive change, intended to be cherry-picked for 16.0.x (ideally
16.0.0, but queued for 16.0.1 if we're too late in the release cycle).

As you can see from the test changes, although the changed logic is
mostly more permissive, it will reject some embedded arch strings that
were accepted before. Because the same logic was previously used for
parsing human-written -march as for the arch attribute (intended to be
stored in normalised form), various short-hand formats were previously
accepted. Maintaining support for such ill-formed attributes would
substantially complicate the logic, and given the previous
implementation was so much stricter in every other way, was surely a bug
rather than a design choice.

Surprisingly, the precise rules for how numbers can be embedded into
extension names isn't fully defined (there is a PR to the ISA manual
that is not yet merged
<https://github.com/riscv/riscv-isa-manual/pull/718>).
In the absence of specific criteria for rejecting extensions names that
would be ambiguous in abbreviated form,
`RISCVISAInfo::parseArchStringNormalized` just pulls out the version
information from the end of each extension description.

Differential Revision: https://reviews.llvm.org/D144353
2023-02-25 06:17:50 +00:00
Fangrui Song
1c417da0f0 Remove uses of ATOMIC_VAR_INIT
ATOMIC_VAR_INIT has a trivial definition `#define ATOMIC_VAR_INIT(value) (value)`,
is deprecated in C17/C++20, and will be removed in newer standards.
2023-02-24 13:43:12 -08:00
Philipp Tomsich
f68f04d07c [RISCV] Add vendor-defined XTheadCondMov (conditional move) extension
The vendor-defined XTheadCondMov (somewhat related to the upcoming
Zicond and XVentanaCondOps) extension add conditional move
instructions with $rd being an input and an ouput instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=73442230966a22b3238b2074691a71d7b4ed914a

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144681
2023-02-24 21:40:42 +01:00
Manolis Tsamis
7b79e8d455 [RISCV] Add vendor-defined XTheadFMemIdx (FP Indexed Memory Operations) extension
The vendor-defined XTHeadFMemIdx (no comparable standard extension exists
at the time of writing) extension adds indexed load/store instructions
for floating-point registers.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=f511f80fa3fcaf6bcbe727fb902b8bd5ec8f9c20

Depends on D144249

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144647
2023-02-24 00:35:37 +01:00
Manolis Tsamis
f6262201d8 [RISCV] Add vendor-defined XTheadMemIdx (Indexed Memory Operations) extension
The vendor-defined XTHeadMemIdx (no comparable standard extension exists
at the time of writing) extension adds indexed load/store instructions
as well as load/store and update register instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=27cfd142d0a7e378d19aa9a1278e2137f849b71b

Depends on D144002

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144249
2023-02-24 00:17:58 +01:00
Benoit Jacob
1215ff89cd Name threadpool threads.
This gives our worker threads some names that allow easily identifying them in tools such as profilers and debuggers.

Differential Revision: https://reviews.llvm.org/D144297
2023-02-23 18:11:15 +00:00
Vitaly Buka
1ddc41c3d1 [clang-format] Fix format of my last patch 2023-02-22 10:12:48 -08:00
Manolis Tsamis
16a6cf6a99 [RISCV] Add vendor-defined XTheadSync (Multi-core synchronization) extension
The vendor-defined XTheadSync (no comparable standard extension exists
at the time of writing) extension adds multi-core synchronization
instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=547c18d9bb95571261dbd17f4767194037eb82bd

Depends on D144496

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144501
2023-02-22 11:15:40 +01:00
Manolis Tsamis
f5b484c56f [RISCV] Add vendor-defined XTheadCmo (Cache Management Operations) extension
The vendor-defined XTHeadCmo (there are some similarities with the
Zicbom standard extension) extension adds cache management instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=a9ba8bc2d396fb8ae2b892f3bc6be8cdfe4b555c

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144496
2023-02-22 10:57:48 +01:00
Vitaly Buka
1b43650c41 [Support] Fix data race with “safe libc++”
Otherwise NFC.
2023-02-21 18:43:37 -08:00
Manolis Tsamis
bbb58a2302 [RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension
The vendor-defined XTHeadMemPair (no comparable standard extension exists
at the time of writing) extension adds two-GPR load/store pair instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=6e17ae625570ff8f3c12c8765b8d45d4db8694bd

Depends on D143847

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144002
2023-02-21 12:21:49 +01:00
Alexandre Ganea
1d0a5f11c0 [Support] Silence warning with Clang ToT.
This fixes the following warning on Windows with latest Clang:
```
[160/3057] Building CXX object lib/Support/CMakeFiles/LLVMSupport.dir/Signals.cpp.obj
In file included from C:/git/llvm-project/llvm/lib/Support/Signals.cpp:260:
C:/git/llvm-project/llvm/lib/Support/Windows/Signals.inc(834,15): warning: comparison of integers of different signs: 'int' and 'unsigned int' [-Wsign-compare]
  if (RetCode == (0xE0000000 | EX_IOERR))
      ~~~~~~~ ^   ~~~~~~~~~~~~~~~~~~~~~
1 warning generated.```
2023-02-20 18:25:20 -05:00
Kazu Hirata
a28b252d85 Use APInt::getSignificantBits instead of APInt::getMinSignedBits (NFC)
Note that getMinSignedBits has been soft-deprecated in favor of
getSignificantBits.
2023-02-19 23:56:52 -08:00