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4 Commits

Author SHA1 Message Date
Kazushi (Jam) Marukawa
40f1e7e804 [VE] Support f128 
Support f128 using VE instructions.  Update regression tests.
I've noticed there is no load or store i128 test, so I add them too.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D86035
 2020-08-17 17:26:52 +09:00
Kazushi (Jam) Marukawa
e981a46a77 [VE] Update lea/load/store instructions 
Summary:
Modify lea/load/store instructions to accept `disp(index, base)`
style addressing mode (called ASX format).  Also, uniform the
number of DAG nodes to have 3 operands for this ASX format
instructions, and update selectADDR functions to lower
appropriate MI.

Reviewers: arsenm, simoll, k-ishizaka

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D76822
 2020-04-06 11:49:46 +02:00
Kazushi (Jam) Marukawa
0fca35c652 [VE] global variable isel patterns 
Summary: Asm expr fixups, isel patterns and tests for global variables addresses.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D73355
 2020-01-24 17:35:14 +01:00
Kazushi (Jam) Marukawa
08ebd8c79e [VE] aligned load/store isel patterns 
Summary:
Aligned load/store isel patterns and tests for
i1/i8/16/32/64 (including extension and truncation) and fp32/64.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D73276
 2020-01-24 15:16:54 +01:00