10628 Commits

Author SHA1 Message Date
Craig Topper
bece74c694 [X86] Add test cases for rndscaless/sd intrinsics.
Also fix the memop in the ins for these instructions. Not sure what effect this has.

llvm-svn: 318624
2017-11-19 06:24:26 +00:00
Craig Topper
512e9e7f3f [X86] Improve load folding of scalar rcp28 and rsqrt28 instructions using sse_load_f32/f64.
llvm-svn: 318623
2017-11-19 05:42:54 +00:00
Craig Topper
9a94dfc457 [X86] Switch cannonlake to use the SkylakeServer scheduling model instead of Haswell.
Cannonlake comes after skylake and supports avx512 so this is probably a closer model for now.

llvm-svn: 318613
2017-11-19 01:25:30 +00:00
Craig Topper
81037f385e [X86] Add skeleton support for icelake CPU.
There are several patches out for review right now to implement Icelake features. This adds a CPU to collect them under.

llvm-svn: 318612
2017-11-19 01:12:00 +00:00
Simon Pilgrim
41fc45c4e6 [X86][AVX512VL] Add AVX512VL tests to the vselect packss tests.
PR34553 has gone, adding tests to ensure it doesn't come back.

vselect_packss_v16i64 still has some awful codegen on AVX512 targets....

llvm-svn: 318599
2017-11-18 19:47:59 +00:00
Craig Topper
65b8a2c9e1 [X86] Add another gather test with v8i8 sign extended indices.
This requires the indices to be legalized and sign extended.

llvm-svn: 318597
2017-11-18 19:25:35 +00:00
Sanjay Patel
c0d1b2ee2e [x86] add tests for unnecessary shuffling; NFC
llvm-svn: 318592
2017-11-18 16:25:38 +00:00
Martin Storsjo
94b59240e2 [X86] Output cfi directives for saved XMM registers even if no GPRs are saved
This makes sure that functions that only clobber xmm registers
(on win64) also get the right cfi directives, if dwarf exceptions
are enabled.

Differential Revision: https://reviews.llvm.org/D40191

llvm-svn: 318591
2017-11-18 06:23:48 +00:00
Simon Pilgrim
7834009726 [X86] Merge scheduling tests for SHLD/SHRD
Reduces spsce used and makes it easier to compare the 2 values for the equivalent instructions

llvm-svn: 318541
2017-11-17 18:35:49 +00:00
Craig Topper
089082378f [X86] Add DAG combine to remove sext i32->i64 from gather/scatter instructions.
Only do this pre-legalize in case we're using the sign extend to legalize for KNL.

This recovers all of the tests that changed when I stopped SelectionDAGBuilder from deleting sign extends.

There's more work that could be done here particularly to fix the i8->i64 test case that experienced split.

llvm-svn: 318468
2017-11-16 23:09:06 +00:00
Craig Topper
1120bb9f59 [X86] Add gather test with index sign extended from i8 type.
Previously SelectionDAGBuilder would remove this sign extend leading to a failure during isel.

The codegen here isn't very nice as we ended up triggering a split.

llvm-svn: 318467
2017-11-16 23:09:03 +00:00
Craig Topper
242374e219 [X86] Don't remove sign extend of gather/scatter indices during SelectionDAGBuilder.
The sign extend might be from an i16 or i8 type and was inserted by InstCombine to match the pointer width. X86 gather legalization isn't currently detecting this to reinsert a sign extend to make things legal.

It's a bit weird for the SelectionDAGBuilder to do this kind of optimization in the first place. With this removed we can at least lean on InstCombine somewhat to ensure the index is i32 or i64.

I'll work on trying to recover some of the test cases by removing sign extends in the backend when its safe to do so with an understanding of the current legalizer capabilities.

This should fix PR30690.

llvm-svn: 318466
2017-11-16 23:08:57 +00:00
Craig Topper
e85ff4f732 [X86] Pre-truncate gather/scatter indices that have element sizes larger than 64-bits before Legalize.
The wider element type will normally cause legalize to try to split and scalarize the gather/scatter, but we can't handle that. Instead, truncate the index early so the gather/scatter node is insulated from the legalization.

This really shouldn't happen in practice since InstCombine will normalize index types to the same size as pointers.

llvm-svn: 318452
2017-11-16 20:23:22 +00:00
Simon Pilgrim
e8e6acdac9 [X86] Add scheduling tests for SHLD/SHRD
llvm-svn: 318402
2017-11-16 14:13:48 +00:00
Craig Topper
46a5d58b8c [X86] Update TTI to report that v1iX/v1fX types aren't legal for masked gather/scatter/load/store.
The type legalizer will try to scalarize these operations if it sees them, but there is no handling for scalarizing them. This leads to a fatal error. With this change they will now be scalarized by the mem intrinsic scalarizing pass before SelectionDAG.

llvm-svn: 318380
2017-11-16 06:02:05 +00:00
Simon Pilgrim
56415772d6 [X86] Add CBW/CDQ/CDQE/CQO/CWD/CWDE to WriteALU schedule class
Some CPUs are already overriding these sign extension instructions but we should be able to use the WriteALU schedule class by default.

Differential Revision: https://reviews.llvm.org/D39899

llvm-svn: 318308
2017-11-15 17:11:24 +00:00
Hans Wennborg
1403100b6b Fix switch-lower-peel-top-case.ll isel pass is not registered error
The test was doing -stop-after=isel, but that pass is actually the
AMDGPUDAGToDAGISel pass, which might not be built when targeting x86_64.
This changes the test to -stop-after=expand-isel-pseudos instead.

Follow-up to r318202.

llvm-svn: 318220
2017-11-14 23:30:28 +00:00
Aditya Nandakumar
e6201c8724 [GISel]: Rework legalization algorithm for better elimination of
artifacts along with DCE

Legalization Artifacts are all those insts that are there to make the
type system happy. Currently, the target needs to say all combinations
of extends and truncs are legal and there's no way of verifying that
post legalization, we only have *truly* legal instructions. This patch
changes roughly the legalization algorithm to process all illegal insts
at one go, and then process all truncs/extends that were added to
satisfy the type constraints separately trying to combine trivial cases
until they converge. This has the added benefit that, the target
legalizerinfo can only say which truncs and extends are okay and the
artifact combiner would combine away other exts and truncs.

Updated legalization algorithm to roughly the following pseudo code.

WorkList Insts, Artifacts;
collect_all_insts_and_artifacts(Insts, Artifacts);

do {
  for (Inst in Insts)
         legalizeInstrStep(Inst, Insts, Artifacts);
  for (Artifact in Artifacts)
         tryCombineArtifact(Artifact, Insts, Artifacts);
} while(!Insts.empty());

Also, wrote a simple wrapper equivalent to SetVector, except for
erasing, it avoids moving all elements over by one and instead just
nulls them out.

llvm-svn: 318210
2017-11-14 22:42:19 +00:00
Rong Xu
dc07ae259e [CodeGen] Fix the test case added in r318202
Add the -mtriple option to filter some platforms.

llvm-svn: 318206
2017-11-14 22:08:37 +00:00
Rong Xu
3573d8da36 [CodeGen] Peel off the dominant case in switch statement in lowering
This patch peels off the top case in switch statement into a branch if the
probability exceeds a threshold. This will help the branch prediction and
avoids the extra compares when lowering into chain of branches.

Differential Revision: http://reviews.llvm.org/D39262

llvm-svn: 318202
2017-11-14 21:44:09 +00:00
Hans Wennborg
e1ecd61b98 Rename CountingFunctionInserter and use for both mcount and cygprofile calls, before and after inlining
Clang implements the -finstrument-functions flag inherited from GCC, which
inserts calls to __cyg_profile_func_{enter,exit} on function entry and exit.

This is useful for getting a trace of how the functions in a program are
executed. Normally, the calls remain even if a function is inlined into another
function, but it is useful to be able to turn this off for users who are
interested in a lower-level trace, i.e. one that reflects what functions are
called post-inlining. (We use this to generate link order files for Chromium.)

LLVM already has a pass for inserting similar instrumentation calls to
mcount(), which it does after inlining. This patch renames and extends that
pass to handle calls both to mcount and the cygprofile functions, before and/or
after inlining as controlled by function attributes.

Differential Revision: https://reviews.llvm.org/D39287

llvm-svn: 318195
2017-11-14 21:09:45 +00:00
Easwaran Raman
0d55b55bb6 [CodeGenPrepare] Disable div bypass when working set size is huge.
Summary:
Bypass of slow divs based on operand values is currently disabled for
-Os. Do the same when profile summary is available and the working set
size of the application is huge. This is similar to how loop peeling is
guarded by hasHugeWorkingSetSize. In the div bypass case, the generated
extra code (and the extra branch) tendss to outweigh the benefits of the
bypass. This results in noticeable performance improvement on an
internal application.

Reviewers: davidxl

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D39992

llvm-svn: 318179
2017-11-14 19:31:51 +00:00
Simon Pilgrim
600174e740 [X86][AVX] Add scheduling test for vmovntdq 256-bit store
Needs to use inline asm as domain will otherwise be changed to float (vmovntps)

llvm-svn: 318151
2017-11-14 14:03:29 +00:00
Craig Topper
c314f461dd [X86] Allow X86ISD::Wrapper to be folded into the base of gather/scatter address
If the base of our gather corresponds to something contained in X86ISD::Wrapper we should be able to fold it into the address.

This patch refactors some of the address matching to more fully use the X86ISelAddressMode struct and the getAddressOperands helper. A new helper function matchVectorAddress is added to call matchWrapper or fall back to matchAddressBase.

We should also be able to support constant offsets from a wrapper, but I'll look into that in a future patch. We may even be able to completely reuse matchAddress here, but I wanted to start simple and work up to it.

Differential Revision: https://reviews.llvm.org/D39927

llvm-svn: 318057
2017-11-13 17:53:59 +00:00
Omer Paparo Bivas
4c679e1435 Inserting a base test for X86 performance nops
Change-Id: I69da08b617d7fae8024c5aee04720eb465f39b81
llvm-svn: 318041
2017-11-13 15:02:39 +00:00
Uriel Korach
2aa707bdaa [X86] test/testn intrinsics lowering to IR. llvm part.
Remove builtins from llvm and add AutoUpgrade support.
Also add fast-isel tests for the TEST and TESTN instructions.

Differential Revision: https://reviews.llvm.org/D38736

llvm-svn: 318036
2017-11-13 12:51:18 +00:00
Jina Nahias
9a7f9f123c [x86][AVX512] Lowering shuffle i/f intrinsics to LLVM IR
This patch, together with a matching clang patch (https://reviews.llvm.org/D38672), implements the lowering of X86 shuffle i/f intrinsics to IR.

Differential Revision: https://reviews.llvm.org/D38671

Change-Id: I1e7d359a74743e995ec356237a85214ce55d3661
llvm-svn: 318026
2017-11-13 09:16:39 +00:00
Gadi Haber
c9f2300652 [X86][SKX] Adding scheduling info of non-intrinsic + commutable SKX opcodes.
Updated the scheduling information of the SKX subtarget  in the file X86SchedSkylakeServer.td under lib/Target/X86 to:
1. add regular opcodes in addition to the suffixed "_Int" opcodes
2. add the (V)MAXCPD/MAXCPS/MAXCSD/MAXCSS/MINCPD/MINCPS/MINCSD/MINCSS
    instructions that are equivalent to their counterparts without the 'C' as they are part of a hack to
    make floating point min/max commutable under fast math.

Reviewers: zvi, RKSimon, craig.topper
Differential Revision: https://reviews.llvm.org/D39833

Change-Id: Ie13702a5ce1b1a08af91ca637a52b6962881e7d6
llvm-svn: 318024
2017-11-13 08:42:07 +00:00
Craig Topper
75d71540f8 [X86] Use sse_load_f32/f64 to improve load folding of scalar vfscalefss/sd, vrcp14ss/sd, rsqrt14ss/sd instructions.
llvm-svn: 318022
2017-11-13 08:07:33 +00:00
Craig Topper
c748455e51 [X86] Regenerate test. NFC
llvm-svn: 318021
2017-11-13 08:07:31 +00:00
Craig Topper
ca8abedb2a [X86] Use sse_load_f32/f64 to improve load folding for scalar VFPCLASS intrinsics.
llvm-svn: 318019
2017-11-13 06:46:48 +00:00
Craig Topper
bf328f263e [X86] Add tests for missed opportunities to fold a 128-bit vector load into vfpclassss and vpfpclasssd.
llvm-svn: 318018
2017-11-13 06:46:46 +00:00
Craig Topper
d4f6094091 [X86] Fix SQRTSS/SQRTSD/RCPSS/RCPSD intrinsics to use sse_load_f32/sse_load_f64 to increase load folding opportunities.
llvm-svn: 318016
2017-11-13 05:25:24 +00:00
Craig Topper
24389c6746 [X86] Add tests for full vector loads to fold-load-unops.ll.
We should be able to fold a full vector load into a scalar intrinsic. Since it's legal to narrow a load.

llvm-svn: 318015
2017-11-13 05:25:23 +00:00
Craig Topper
a95a1fd42d [X86] Regenerate fold-load-unops.ll and add and avx512f command line.
llvm-svn: 318014
2017-11-13 05:25:21 +00:00
Craig Topper
deee24b83c [X86] Use sse_load_f32/f64 in patterns for the memory forms of VRNDSCALESS/SD.
llvm-svn: 318009
2017-11-13 02:03:01 +00:00
Craig Topper
63157c4784 [X86] Use EVEX encoded VRNDSCALE instructions to implement the legacy round intrinsics.
The VRNDSCALE instructions implement a superset of the (V)ROUND instructions. They are equivalent if the upper 4-bits of the immediate are 0.

This patch lowers the legacy intrinsics to the VRNDSCALE ISD node and masks the upper bits of the immediate to 0. This allows us to take advantage of the larger register encoding space.

We should maybe consider converting VRNDSCALE back to VROUND in the EVEX to VEX pass if the extended registers are not being used.

I notice some load folding opportunities being missed for the VRNDSCALESS/SD instructions that I'll try to fix in future patches.

llvm-svn: 318008
2017-11-13 02:03:00 +00:00
Craig Topper
b42a23ff8f [X86] Add an X86ISD::RANGES opcode to use for the scalar intrinsics.
This fixes a bug where we selected packed instructions for scalar intrinsics.

llvm-svn: 317999
2017-11-12 18:51:09 +00:00
Craig Topper
6b53c4a982 [X86] Add test cases and command lines demonstrating how we accidentally select vrangeps/vrangepd from vrangess/vrangesd instrinsics when the rounding mode is CUR_DIRECTION
llvm-svn: 317998
2017-11-12 18:51:08 +00:00
Craig Topper
ac250825c6 [X86] Use vrndscaleps/pd for 128/256 ffloor/ftrunc/fceil/fnearbyint/frint when avx512vl is enabled.
This matches what we do for scalar and 512-bit types.

llvm-svn: 317991
2017-11-11 21:44:51 +00:00
Craig Topper
ae9ffa1f5a [X86] Remove avx512-round.ll. The 512-bit rounding tests are now in vec_floor.ll with 128/256 sizes.
llvm-svn: 317990
2017-11-11 21:44:50 +00:00
Craig Topper
e44fc7836e [X86] Add avx512vl command line to vec_floor.ll. Add 512-bit test cases.
llvm-svn: 317989
2017-11-11 21:44:49 +00:00
Craig Topper
a9f48803d7 [X86] Add avx512f command line to rounding-ops.ll
llvm-svn: 317988
2017-11-11 21:44:48 +00:00
Craig Topper
1a20db2108 [X86] Regenerate rounding-ops.ll with update_llc_test_checks.py
llvm-svn: 317987
2017-11-11 21:44:47 +00:00
Craig Topper
0ccec70ff5 [X86] Add scalar register class versions of VRNDSCALE instructions and rename the existing versions to _Int.
This is consistent with out normal implementation of scalar instructions.

While there disable load folding for the patterns with IMPLICIT_DEF unless optimizing for size which is also our standard practice.

llvm-svn: 317977
2017-11-11 08:24:15 +00:00
Craig Topper
4d80c5dafc [X86] Regenerate avx512-round.ll test.
llvm-svn: 317976
2017-11-11 08:24:13 +00:00
Craig Topper
1a093934a9 [X86] Set the execution domain for vptest instruction to the integer domain.
llvm-svn: 317973
2017-11-11 06:19:12 +00:00
Craig Topper
0eb4a43384 [X86] Correct the execution domain on ROUND/VROUND instructions.
llvm-svn: 317968
2017-11-11 02:26:05 +00:00
Craig Topper
ffd48e3c27 [SelectionDAG] Teach SelectionDAGBuilder's getUniformBase for gather/scatter handling to accept GEPs with more than 2 operands if the middle operands are all 0s
Currently we can only get a uniform base from a simple GEP with 2 operands. This causes us to miss address folding opportunities for simple global array accesses as the test case shows.

This patch adds support for larger GEPs if the other indices are 0 since those don't require any additional computations to be inserted.

We may also want to handle constant splats of zero here, but I'm leaving that for future work when I have a real world example.

Differential Revision: https://reviews.llvm.org/D39911

llvm-svn: 317947
2017-11-10 22:50:50 +00:00
Craig Topper
cad1c95b31 [X86] Add test case to demonstrate failure to fold the address computation of a simple gather from a global array. NFC
llvm-svn: 317905
2017-11-10 18:48:18 +00:00