Adding the td definitions, and their associated assembly and disassembly
test cases for the decimal floating point test instructions defined in
section 5.6.3 of ISA 3.1
Reviewed By: lei, amyk
Differential Revision: https://reviews.llvm.org/D154606
Add td definitions and asm/disasm tests for the dfp format
instructions in ISA 3.1 section 5.6.6
Reviewed By: stefanp, kamaub
Differential Revision: https://reviews.llvm.org/D154465
Add td definitions and asm/disasm tests for the quantum conversion
instructions in ISA 3.1 section 5.6.5
Reviewed By: stefanp
Differential Revision: https://reviews.llvm.org/D154394
Add td definitions and asm/disasm tests for the quantum adjustment
instructions in ISA 3.1 section 5.6.4
Reviewed By: stefanp
Differential Revision: https://reviews.llvm.org/D154369
This patch adds the DFP mul and div instructions. This includes both the
double and quad forms of the instructions as well as the record form.
Reviewed By: amyk
Differential Revision: https://reviews.llvm.org/D150787
Add the following Decimal Floating Point (DFP) instructions for PowerPC.
dadd, daddq, dsub, dsubq
In order to add these instructions a new register class for a pair
of floating point registers is added.
This patch is only to allow the user to specify the instructions in
assembly. There is no scheduling or patterns for the instructions.
Reviewed By: amyk
Differential Revision: https://reviews.llvm.org/D148597
