Adding clauses to `CodeGenFunction::EmitX86BuiltinExpr` to convert
SSE4.1/AVX1 builts `roundps/pd/ss/sd` to regular rounding modes.
We use:
1. `roundeven/floor/ceil/trunc` when not using MXCSR or _MM_FROUND_RAISE_EXC , and FP mode is not strict,
2. `experimental_constrained_roundeven/floor/ceil/trunc` when not using MXCSR or _MM_FROUND_RAISE_EXC , and FP mode is strict
3. `x86_sse41/avx_round_ps/pd/ss/sd` when using MXCSR or _MM_FROUND_RAISE_EXC .
Closes#170273
Let standard casting / builtin_convertvector handle the conversions from BF16 to F32
My only query is how to best implement _mm_cvtpbh_ps - I went for the
v8bf16 -> v8f32 conversion followed by subvector extraction in the end,
but could just as easily extract a v4bf16 first - makes no difference to
final optimized codegen.
First part of #154911
Now that #152455 is done, we can make all the scalar fma intrinsics to
wrap __builtin_elementwise_fma, which also allows constexpr
The main difference is that FMA4 intrinsics guarantee that the upper
elements are zero, while FMA3 passes through the destination register
elements like older scalar instructions
Fixes#154555
Per Intel Architecture Instruction Set Extensions Programming Reference
rev. 59 (https://cdrdv2.intel.com/v1/dl/getContent/671368), Revision
History entry for revision -59, AMX-TRANSPOSE was removed
As noted on #156494 and #157403 - its much easier to work with the byte
shift intrinsics if we treat them as vXi8 types instead of vXi64 types
which will require bitcasting
We already do this for the PALIGNR intrinsics which are a more advanced
version of the same shuffle
The following avx512 intrinsics were removed:
- `__builtin_ia32_vplzcntd_128`
- `__builtin_ia32_vplzcntd_256`
- `__builtin_ia32_vplzcntd_512`
- `__builtin_ia32_vplzcntq_128`
- `__builtin_ia32_vplzcntq_256`
- `__builtin_ia32_vplzcntq_512`
Users of the removed intrinsics (e.g. `_mm512_lzcnt_epi64`,
`_mm_lzcnt_epi32`) are now relying on `__builtin_elementwise_ctlz` and
are marked as `constexpr`.
Fixes: #154279
Replaces the XOP/AVX512 per-element rotation/funnel shift builtins with the generic __builtin_elementwise_fshl/fshr
We still have uniform immediate variants to handle next.
Part of #153152
The following intrinsics were replaced by a combination of
`__builtin_shufflevector` and `__builtin_convertvector`:
- `__builtin_ia32_vcvtph2ps`
- `__builtin_ia32_vcvtph2ps256`
Fixes#152749
The following intrinsics were replaced by `__builtin_elementwise_fma`:
- `__builtin_ia32_vfmaddps(256)`
- `__builtin_ia32_vfmaddpd(256)`
- `__builtin_ia32_vfmaddph(256)`
- `__builtin_ia32_vfmaddbf16(128 | 256 | 512)`
All the aforementioned `__builtin_ia32_vfmadd*` intrinsics are
equivalent to a `__builtin_elementwise_fma`, so keeping them is an
unnecessary indirection.
Fixes [#152461](https://github.com/llvm/llvm-project/issues/152461)
---------
Co-authored-by: Simon Pilgrim <llvm-dev@redking.me.uk>
clang/lib/CodeGen/CGBuiltin.cpp is over 1MB long (>23k LoC), and can
take minutes to recompile (depending on compiler and host system) when
modified, and 5 seconds for clangd to update for every edit. Splitting
this file was discussed in this thread:
https://discourse.llvm.org/t/splitting-clang-s-cgbuiltin-cpp-over-23k-lines-long-takes-1min-to-compile/
and the idea has received a number of +1 votes, hence this change.
