This bug seems to have been exposed by the combined m->m load/store
instructions available on M68k (these instructions are not available on
i386, which the M68k backend is based on). This meant that token factors
were inserted which could lead to distinct call sequence chains,
increasing the nesting level and preventing the matching callseq_start
from being identified during scheduling.
The patch addresses this by not allowing combined loads/stores when the
folded operation would result in a new chain dependency on a different
call sequence.
closes#146213 and #175472
M68k's SETCC instruction (`scc`) distinctly fills the destination byte
with all 1s. If boolean contents are set to `ZeroOrOneBooleanContent`,
LLVM can mistakenly think the destination holds `0x01` instead of `0xff`
and emit broken code as a result. This change corrects the boolean
content type to `ZeroOrNegativeOneBooleanContent`.
For example, this IR:
```llvm
define dso_local signext range(i8 0, 2) i8 @testBool(i32 noundef %a) local_unnamed_addr #0 {
entry:
%cmp = icmp eq i32 %a, 4660
%. = zext i1 %cmp to i8
ret i8 %.
}
```
would previously build as:
```asm
testBool: ; @testBool
cmpi.l #4660, (4,%sp)
seq %d0
and.l #255, %d0
rts
```
Notice the `zext` is erroneously not clearing the low bits, and thus the
register returns with 255 instead of 1. This patch fixes the issue:
```asm
testBool: ; @testBool
cmpi.l #4660, (4,%sp)
seq %d0
and.l #1, %d0
rts
```
Most of the tests containing `scc` suffered from the same value error as
described above, so those tests have been updated to match the new
output (which also logically corrects them).
Had been doing this piece by piece, but makes more sense to do it in a
single PR. Adds support for `ARID`, `PCI`, `PCD`, `AL`, and `ARD`
addressing modes for atomic operations, along with a variety of tests.
The `CodeModel` tests have been rearranged, as some of the new
addressing modes are only exercised under some combinations of
`CodeModel` and relocation mode
