5 Commits

Author SHA1 Message Date
Sam Elliott
1eebd2a42e
[RISCV] Mark Xqccmp as not experimental (#175066) 2026-01-10 07:50:29 -08:00
Philip Reames
58df9b1a01
[RISCV] Enable LUi/AUIPC+ADDI/ADDIW reg alloc hint by default (#155693)
This block of code is currently conditional on the fusions being enabled
but as far as I can tell, does no harm to generally enable. The net
effect is the generically compiled code runs slightly better on machines
with this fusion.

The actual motivation is merely to stop confusing myself when I see the
sequence in code; the register allocators choice to sometimes blow two
registers instead of one is just generally weird, and my eyes spot it
when scanning disassembly.

(Note that this is just the regalloc hint; the scheduling changes remain
conditional, and probably should remain so.)
2025-08-27 15:59:08 -07:00
Iris Shi
dae5c4e1e7
[RISCV] Expand constant multiplication for targets without M extension (#137195)
Closes #137023

On RISC-V machines without a native multiply instruction (e.g., `rv32i`
base), multiplying a variable by a constant integer often compiles to a
call to a library routine like `__mul{s,d}i3`.

```assembly
	.globl __mulxi3
	.type  __mulxi3, @function
__mulxi3:
	mv     a2, a0
	mv     a0, zero
.L1:
	andi   a3, a1, 1
	beqz   a3, .L2
	add    a0, a0, a2
.L2:
	srli   a1, a1, 1
	slli   a2, a2, 1
	bnez   a1, .L1
	ret
```

This library function implements multiplication in software using a loop
of shifts and adds, processing the constant bit by bit. On rv32i, it
requires a minimum of 8 instructions (for multiply by `0`) and up to
about 200 instructions (by `0xffffffff`), involves heavy branching and
function call overhead.

When not optimizing for size, we could expand the constant
multiplication into a sequence of shift and add/sub instructions. For
now we use non-adjacent form for the shift and add/sub sequence, which
could save 1/2 - 2/3 instructions compared to a shl+add-only sequence.
2025-05-16 09:40:11 +08:00
Craig Topper
fc7fee8360
Revert "[RISCV] Allow spilling to unused Zcmp Stack (#125959)" (#137060)
This reverts commit 50cdf6cbc5035345507bb4d23fcb0292272754eb.

This patch causes miscompiles with vector and produces some odd code for
ilp32e.
2025-04-23 17:36:00 -07:00
Sam Elliott
e49180d84c
[RISCV] Xqccmp Code Generation (#128815)
This adds support for Xqccmp to the following passes:
- Prolog Epilog Insertion - reusing much of the existing push/pop logic,
but extending it to cope with frame pointers and reorder the CFI
information correctly.
- Move Merger - extending it to support the `qc.` variants of the
double-move instructions.
- Push/Pop Optimizer - extending it to support the `qc.` variants of the
pop instructions.

The testing is based on existing Zcmp tests, but I have put them in
separate files as some of the Zcmp tests were getting quite long.
2025-03-05 10:59:45 -08:00