2 Commits

Author	SHA1	Message	Date
Phoebe Wang	94b164c218	[X86][AVX10] Remove EVEX512 and AVX10-256 implementations (#157034) ... The 256-bit maximum vector register size control was removed from AVX10 whitepaper, ref: https://cdrdv2.intel.com/v1/dl/getContent/784343 We have warned these options in LLVM21 through #132542. This patch removes underlying implementations in LLVM22.	2025-09-05 14:08:59 +00:00
Han-Kuan Chen	d02a704ec9	[SLP][REVEC] Make getExtractWithExtendCost support FixedVectorType as Dst. (#134822)	2025-04-10 18:54:45 +08:00