583 Commits

Author SHA1 Message Date
Sergei Barannikov
5f3eab9e45
[AVR] Remove extra ROL / ROR operands (#117510)
The nodes have one input, shift amount of 1 is implied.
2024-11-25 05:15:20 +03:00
Sergei Barannikov
c85c77c054
[AVR] Fix shift node descriptions (#117456)
Wide shift nodes produce two results, not one.
Reuse the added type profile to define the standard "shift parts" nodes.
2024-11-24 09:26:52 +03:00
Sergei Barannikov
e131b0d241
[SelectionDAG] Fix some SDNode type mismatches between *.td files and ISel (#117375)
This removes operands/results either in SDNode description or in ISel
code so that they match each other.
2024-11-23 00:51:42 +03:00
Nikita Popov
2e07c2b1bf [AVR] Use getSignedConstant() for negative number 2024-11-22 14:57:30 +01:00
Kazu Hirata
ed8019d9fb
[Target] Remove unused includes (NFC) (#116577)
Identified with misc-include-cleaner.
2024-11-18 07:19:50 -08:00
Matin Raayai
bb3f5e1fed
Overhaul the TargetMachine and LLVMTargetMachine Classes (#111234)
Following discussions in #110443, and the following earlier discussions
in https://lists.llvm.org/pipermail/llvm-dev/2017-October/117907.html,
https://reviews.llvm.org/D38482, https://reviews.llvm.org/D38489, this
PR attempts to overhaul the `TargetMachine` and `LLVMTargetMachine`
interface classes. More specifically:
1. Makes `TargetMachine` the only class implemented under
`TargetMachine.h` in the `Target` library.
2. `TargetMachine` contains target-specific interface functions that
relate to IR/CodeGen/MC constructs, whereas before (at least on paper)
it was supposed to have only IR/MC constructs. Any Target that doesn't
want to use the independent code generator simply does not implement
them, and returns either `false` or `nullptr`.
3. Renames `LLVMTargetMachine` to `CodeGenCommonTMImpl`. This renaming
aims to make the purpose of `LLVMTargetMachine` clearer. Its interface
was moved under the CodeGen library, to further emphasis its usage in
Targets that use CodeGen directly.
4. Makes `TargetMachine` the only interface used across LLVM and its
projects. With these changes, `CodeGenCommonTMImpl` is simply a set of
shared function implementations of `TargetMachine`, and CodeGen users
don't need to static cast to `LLVMTargetMachine` every time they need a
CodeGen-specific feature of the `TargetMachine`.
5. More importantly, does not change any requirements regarding library
linking.

cc @arsenm @aeubanks
2024-11-14 13:30:05 -08:00
Sergei Barannikov
501a583441
[TableGen][SelectionDAG] Remove the implicit DAG node (#115295)
The node was introduced in 59c39dc1 and was intended to allow writing
patterns like this:
`[(set AL, (mul AL, GR8:$src1)), (implicit EFLAGS)]`

However, it does not introduce new functionality because the same
pattern can be equivalently expressed as:
`[(set AL, EFLAGS, (mul AL, GR8:$src1))]`

The latter form is also more flexible as it allows reordering output
operands.

In most places uses of `implicit` were redundant -- removing them didn't
change anything in the generated DAG tables. The only three cases where
it did have effect are in X86InstrArithmetic.td and X86InstrSystem.td --
those were rewritten to use `set` node.

Removing `implicit` from some patterns made them importable by GISel,
hence the change in a test.
2024-11-09 07:25:40 +03:00
Sergei Barannikov
eeb987f6f3
[MC] Make generated MCInstPrinter::getMnemonic const (NFC) (#114682)
The value returned from the function depends only on the instruction opcode.

As a drive-by, change the type of the argument to const-reference.
2024-11-03 20:37:26 +03:00
Alex Rønne Petersen
ad4a582fd9
[llvm] Consistently respect naked fn attribute in TargetFrameLowering::hasFP() (#106014)
Some targets (e.g. PPC and Hexagon) already did this. I think it's best
to do this consistently so that frontend authors don't run into
inconsistent results when they emit `naked` functions. For example, in
Zig, we had to change our emit code to also set `frame-pointer=none` to
get reliable results across targets.

Note: I don't have commit access.
2024-10-18 09:35:42 +04:00
Craig Topper
af629ec2d4 [AVR] Use MCRegister. NFC 2024-09-28 11:40:26 -07:00
Ben Shi
8c3b94f420
[AVR][MC] Fix incorrect range of relative jumps (#109124)
'rjmp .+4094' is legal but rejected by llvm-mc since
86a60e7f1e8f361f84ccb6e656e848dd4fbaa713, and this patch fixed that
range issue.
2024-09-20 11:40:07 +08:00
Lei Huang
4b524088a8
[NFC] Update function names in MCTargetAsmParser.h (#108643)
Update function names to adhere to LLVM coding standard.
2024-09-18 11:43:49 -04:00
Craig Topper
55808d8467 [AVR] Use MCRegister in AsmParser. NFC 2024-09-17 08:45:29 -07:00
Patryk Wychowaniec
86a60e7f1e
[AVR] Fix parsing & emitting relative jumps (#106722)
Ever since 6859685a87ad093d60c8bed60b116143c0a684c7 (or, precisely,
84428dafc0941e3a31303fa1b286835ab2b8e234) relative jumps emitted by the
AVR codegen are off by two bytes - this pull request fixes it.

## Abstract

As compared to absolute jumps, relative jumps - such as rjmp, rcall or
brsh - have an implied `pc+2` behavior; that is, `jmp 100` is `pc =
100`, but `rjmp 100` gets understood as `pc = pc + 100 + 2`.

This is not reflected in the AVR codegen:


f95026dbf6/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp (L89)

... which always emits relative jumps that are two bytes too far - or
rather it _would_ emit such jumps if not for this check:


f95026dbf6/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp (L517)

... which causes most of the relative jumps to be actually resolved
late, by the linker, which applies the offsetting logic on its own,
hiding the issue within LLVM.

[Some time
ago](697a162fa6)
we've had a similar "jumps are off" problem that got solved by touching
`shouldForceRelocation()`, but I think that has worked only by accident.
It's exploited the fact that absolute vs relative jumps in the parsed
assembly can be distinguished through a "side channel" check relying on
the existence of labels (i.e. absolute jumps happen to named labels, but
relative jumps are anonymous, so to say). This was an alright idea back
then, but it got broken by 6859685a87ad093d60c8bed60b116143c0a684c7.

I propose a different approach:
- when emitting relative jumps, offset them by `-2` (well, `-1`,
strictly speaking, because those instructions rely on right-shifted
offset),
- when parsing relative jumps, treat `.` as `+2` and read `rjmp .+1234`
as `rjmp (1234 + 2)`.

This approach seems to be sound and now we generate the same assembly as
avr-gcc, which can be confirmed with:

```cpp
// avr-gcc test.c -O3 && avr-objdump -d a.out

int main() {
    asm(
"      foo:\n\t"
"        rjmp  .+2\n\t"
"        rjmp  .-2\n\t"
"        rjmp  foo\n\t"
"        rjmp  .+8\n\t"
"        rjmp  end\n\t"
"        rjmp  .+0\n\t"
"      end:\n\t"
"        rjmp .-4\n\t"
"        rjmp .-6\n\t"
"      x:\n\t"
"        rjmp x\n\t"
"        .short 0xc00f\n\t"
);
}
```

avr-gcc is also how I got the opcodes for all new tests like `inst-brbc.s`, so we should be good.
2024-08-30 15:25:54 +02:00
Patryk Wychowaniec
c7a4efa429
[AVR] Fix 16-bit LDDs with immediate overflows (#104923)
16-bit loads are expanded into a pair of 8-bit loads, so the maximum
offset of such 16-bit loads must be 62, not 63.
2024-08-29 15:28:17 +08:00
Piyou Chen
b01c006f73
[TII][RISCV] Add renamable bit to copyPhysReg (#91179)
The renamable flag is useful during MachineCopyPropagation but renamable
flag will be dropped after lowerCopy in some case.

This patch introduces extra arguments to pass the renamable flag to
copyPhysReg.
2024-08-27 10:08:43 +08:00
Sergei Barannikov
25bea3eb03
[MC] Forward declare ELFObjectWriter (#100989) 2024-07-30 10:40:40 +03:00
Fangrui Song
c473e75ade MCAssmembler: Move ELFHeaderEFlags to ELFObjectWriter
Now that MCELFStreamer can access ELFObjectWriter (commit
70c52b62c5669993e341664a63bfbe5245e32884), we can move ELFHeaderEFlags
there.
2024-07-22 18:20:18 -07:00
Fangrui Song
6717dc5c47 *AsmBackend.cpp: Include StringSwitch.h
They currently get the header from MCLinkerOptimizationHint.h, which
will be removed from MCAssembler.h.
2024-07-21 11:17:19 -07:00
Fangrui Song
8f14e39e59 [MC] Remove unnecessary isVerboseAsm from Target::AsmTargetStreamerCtorTy
The parameter is confusing as it duplicates MCStreamer::isVeboseAsm
(initialized from MCTargetOptions::AsmVerbose). After
233cca169237b91d16092c82bd55ee6a283afe98, no in-tree target uses the
parameter.
2024-07-21 10:19:17 -07:00
Joseph Huber
3f1a767572
[LLVM] Factor disabled Libcalls into the initializer (#98421)
Summary:
These Libcalls represent which functions are available to the backend.
If a runtime call is not available, the target sets the the name to
`nullptr`. Currently, this logic is spread around the various targets.
This patch pulls all of the locations that disable libcalls into the
intializer. This patch is effectively NFC.

The motivation behind this patch is that currently the LTO handling uses
the list of all runtime calls to determine which functions cannot be
internalized and must be extracted from static libraries. We do not want
this to happen for libcalls that are not emitted by the backend. A
follow-up patch will move out this logic so the LTO pass can know which
rtlib calls are actually used by the backend.
2024-07-11 12:59:25 -05:00
Fangrui Song
e94a00c3b8 [MC] Use a stub ctor for MCAsmLayout
and replace MCAssembler::Layout with a bool.
This mostly completes "[MC] Start merging MCAsmLayout into MCAssembler".

Note: BOLT used a dummy `MCAsmLayout` to call `getSymbolOffset`, which
is technically not supported. There is some discussion in
https://reviews.llvm.org/D154604 .

The revert f80a4072ced41b52363c63df28fea9a649f7f89e is incorrect and
actually broke bots.
2024-07-02 10:10:31 -07:00
Davide Italiano
f80a4072ce Revert "[MC] Use a stub ctor for MCAsmLayout"
This reverts commit bbb50369a149d9a7d1f91efaaabf75c260a220c7.

This breaks BOLT.
2024-07-02 08:54:18 -07:00
Fangrui Song
bbb50369a1 [MC] Use a stub ctor for MCAsmLayout
and replace MCAssembler::Layout with a bool.
This mostly completes "[MC] Start merging MCAsmLayout into MCAssembler".
2024-07-01 18:04:27 -07:00
Fangrui Song
057f28be3e [MC] Remove unused MCAsmLayout declarations and includes 2024-07-01 17:47:13 -07:00
Fangrui Song
e25e8003ca MCExpr::evaluateAsRelocatable: replace the MCAsmLayout parameter with MCAssembler
Continue the MCAsmLayout removal work started by 67957a45ee1ec42ae1671cdbfa0d73127346cc95.
2024-07-01 16:23:43 -07:00
Fangrui Song
88c0a82588 [MC] Make MCAsmBackend::fixupNeedsRelaxation not pure virtual
This hook only needs to be implemented if mayNeedRelaxation may return
true.
2024-07-01 13:46:30 -07:00
Nikita Popov
4169338e75
[IR] Don't include Module.h in Analysis.h (NFC) (#97023)
Replace it with a forward declaration instead. Analysis.h is pulled in
by all passes, but not all passes need to access the module.
2024-06-28 14:30:47 +02:00
Ben Shi
090e0c4f50
[AVR][NFC] Improve format of target description files (#96449) 2024-06-24 16:52:13 +08:00
Kazu Hirata
e773f5307d
[AVR] Let ArrayRef infer the array size (NFC) (#96076) 2024-06-19 08:13:22 -07:00
Matt Arsenault
5c9352eb02
DAG: Replace bitwidth with type in suffix in atomic tablegen ops (#94845) 2024-06-13 11:52:22 +02:00
paperchalice
7652a59407
Reland "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94149)
- Fix build with `EXPENSIVE_CHECKS`
- Remove unused `PassName::ID` to resolve warning
- Mark `~SelectionDAGISel` virtual so AArch64 backend can work properly
2024-06-04 08:10:58 +08:00
paperchalice
8917afaf0e
Revert "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94146)
This reverts commit de37c06f01772e02465ccc9f538894c76d89a7a1 to
de37c06f01772e02465ccc9f538894c76d89a7a1

It still breaks EXPENSIVE_CHECKS build. Sorry.
2024-06-02 14:31:52 +08:00
paperchalice
de37c06f01
[Targets] Remove unused ID in *DAGToDAGISel (#94135) 2024-06-02 10:27:50 +08:00
paperchalice
d2cdc8ab45
[NewPM][CodeGen] Port selection dag isel to new pass manager (#83567)
Port selection dag isel to new pass manager.
Only `AMDGPU` and `X86` support new pass version. `-verify-machineinstrs` in new pass manager belongs to verify instrumentation, it is enabled by default.
2024-06-02 09:12:33 +08:00
Ben Shi
50da7680d8
[AVR][NFC] Improve format of target description files (#91296) 2024-05-07 16:42:46 +08:00
luolent
a98a6e95be
Add clarifying parenthesis around non-trivial conditions in ternary expressions. (#90391)
Fixes [#85868](https://github.com/llvm/llvm-project/issues/85868)

Parenthesis are added as requested on ternary operators with non trivial conditions.

I used this [precedence table](https://en.cppreference.com/w/cpp/language/operator_precedence) for reference, to make sure we get the expected behavior on each change.
2024-05-04 18:38:45 +01:00
Fangrui Song
4e34035616 [MC] Remove RelaxAll parameters from create*Streamer
Related to clean-up opportunities discussed at #90013.

After these cleanups, the `RelaxAll` parameter from
`createMCObjectStreamer` can be removed as well. As
`createMCObjectStreamer` is a more user-facing API and used by two files
in mlir/, we postpone the cleanup to the future.
2024-04-25 14:57:27 -07:00
Kazu Hirata
c37c472597
[AVR] Let ArrayRef infer the array size (NFC) (#88638) 2024-04-18 09:27:24 -07:00
Ben Shi
9dbd364589
[AVR][NFC] Improve format of target description files (#87212) 2024-04-02 08:38:02 +08:00
Sergei Barannikov
5e5b656102
[MC] Make MCParsedAsmOperand::getReg() return MCRegister (#86444) 2024-03-25 05:13:48 +03:00
Patryk Wychowaniec
328cb9b731
[AVR] Remove earlyclobber from LDDRdPtrQ (#85277)
LDDRdPtrQ was marked as `earlyclobber`, which doesn't play well with
GreedyRA (which can generate this instruction through `loadRegFromStackSlot()`).

This seems to be the same case as:

a99b912c9b/llvm/lib/Target/AVR/AVRInstrInfo.td (L1421)

Closes https://github.com/llvm/llvm-project/issues/81911.
2024-03-15 19:07:54 +08:00
Ben Shi
3d14e85578
[AVR][NFC] Reformat target description files (#83755) 2024-03-04 16:09:32 +08:00
Sergei Barannikov
1e4c76cdc9
[MC][AsmParser] Make MatchRegisterName return MCRegister (NFC) (#81408)
`MCRegister` is preferred over `unsigned` nowadays.
2024-02-18 13:59:49 +03:00
Philip Reames
3ff7caea33
[TTI] Use Register in isLoadFromStackSlot and isStoreToStackSlot [nfc] (#80339) 2024-02-01 17:52:35 -08:00
Alex Bradbury
197214e39b
[RFC][SelectionDAG] Add and use SDNode::getAsZExtVal() helper (#76710)
This follows on from #76708, allowing
`cast<ConstantSDNode>(N)->getZExtValue()` to be replaced with just
`N->getAsZextVal();`
    
Introduced via `git grep -l "cast<ConstantSDNode>\(.*\).*getZExtValue" |
xargs sed -E -i
's/cast<ConstantSDNode>\((.*)\)->getZExtValue/\1->getAsZExtVal/'` and
then using `git clang-format` on the result.
2024-01-09 12:25:17 +00:00
Alex Bradbury
80aeb62211
[llvm][NFC] Use SDValue::getConstantOperandVal(i) where possible (#76708)
This helper function shortens examples like
`cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();` to
`Node->getConstantOperandVal(1);`.

Implemented with:
`git grep -l
"cast<ConstantSDNode>\(.*->getOperand\(.*\)\)->getZExtValue\(\)" | xargs
sed -E -i

's/cast<ConstantSDNode>\((.*)->getOperand\((.*)\)\)->getZExtValue\(\)/\1->getConstantOperandVal(\2)/`
and `git grep -l
"cast<ConstantSDNode>\(.*\.getOperand\(.*\)\)->getZExtValue\(\)" | xargs
sed -E -i

's/cast<ConstantSDNode>\((.*)\.getOperand\((.*)\)\)->getZExtValue\(\)/\1.getConstantOperandVal(\2)/'`.
With a couple of simple manual fixes needed. Result then processed by
`git clang-format`.
2024-01-02 13:14:28 +00:00
Kazu Hirata
586ecdf205
[llvm] Use StringRef::{starts,ends}_with (NFC) (#74956)
This patch replaces uses of StringRef::{starts,ends}with with
StringRef::{starts,ends}_with for consistency with
std::{string,string_view}::{starts,ends}_with in C++20.

I'm planning to deprecate and eventually remove
StringRef::{starts,ends}with.
2023-12-11 21:01:36 -08:00
Craig Topper
e87f33d9ce
[RISCV][MC] Pass MCSubtargetInfo down to shouldForceRelocation and evaluateTargetFixup. (#73721)
Instead of using the STI stored in RISCVAsmBackend, try to get it from
the MCFragment.

This addresses the issue raised here
https://discourse.llvm.org/t/possible-problem-related-to-subtarget-usage/75283
2023-12-07 13:17:58 -08:00
Kazu Hirata
92c2529ccd [llvm] Stop including vector (NFC)
Identified with clangd.
2023-12-03 22:32:21 -08:00