Following discussions in #110443, and the following earlier discussions
in https://lists.llvm.org/pipermail/llvm-dev/2017-October/117907.html,
https://reviews.llvm.org/D38482, https://reviews.llvm.org/D38489, this
PR attempts to overhaul the `TargetMachine` and `LLVMTargetMachine`
interface classes. More specifically:
1. Makes `TargetMachine` the only class implemented under
`TargetMachine.h` in the `Target` library.
2. `TargetMachine` contains target-specific interface functions that
relate to IR/CodeGen/MC constructs, whereas before (at least on paper)
it was supposed to have only IR/MC constructs. Any Target that doesn't
want to use the independent code generator simply does not implement
them, and returns either `false` or `nullptr`.
3. Renames `LLVMTargetMachine` to `CodeGenCommonTMImpl`. This renaming
aims to make the purpose of `LLVMTargetMachine` clearer. Its interface
was moved under the CodeGen library, to further emphasis its usage in
Targets that use CodeGen directly.
4. Makes `TargetMachine` the only interface used across LLVM and its
projects. With these changes, `CodeGenCommonTMImpl` is simply a set of
shared function implementations of `TargetMachine`, and CodeGen users
don't need to static cast to `LLVMTargetMachine` every time they need a
CodeGen-specific feature of the `TargetMachine`.
5. More importantly, does not change any requirements regarding library
linking.
cc @arsenm @aeubanks
SPARC ABI doesn't use stack realignment, so let LLVM know about it in
`SparcFrameLowering`. This has the side effect of making all overaligned
allocations go through `LowerDYNAMIC_STACKALLOC`, so implement the
missing logic there too for overaligned allocations.
This makes the SPARC backend not crash on overaligned `alloca`s and fix
https://github.com/llvm/llvm-project/issues/89569.
Some targets (e.g. PPC and Hexagon) already did this. I think it's best
to do this consistently so that frontend authors don't run into
inconsistent results when they emit `naked` functions. For example, in
Zig, we had to change our emit code to also set `frame-pointer=none` to
get reliable results across targets.
Note: I don't have commit access.
Add support for using a thread-local variable with a specified offset
for holding the stack guard canary value. This supports both 32- and 64-
bit PowerPC targets.
This mirrors changes from #108942 but targeting PowerPC instead of
RISCV. Because both of these PRs modify the same driver functions, this
series is stack on top of the RISC-V one.
---------
Signed-off-by: Keith Packard <keithp@keithp.com>
The renamable flag is useful during MachineCopyPropagation but renamable
flag will be dropped after lowerCopy in some case.
This patch introduces extra arguments to pass the renamable flag to
copyPhysReg.
This patch adds a pass that provides workarounds for the errata
described in GRLIB-TN-0009, GRLIB-TN-0010, GRLIB-TN-0011, GRLIB-TN-0012,
and GRLIB-TN-0013, that are applicable to the GR712RC and UT700. The
documents are available for download from here:
https://www.gaisler.com/index.php/information/app-tech-notes
The pass will detect certain sensitive instruction sequences and prevent
them from occurring by inserting NOP instruction. Below is an overview
of each of the workarounds. A similar implementation is available in
GCC.
GRLIB-TN-0009:
* Insert NOPs to prevent the sequence (stb/sth/st/stf) -> (single
non-store/load instruction) -> (any store)
* Insert NOPs to prevent the sequence (std/stdf) -> (any store)
GRLIB-TN-0010:
* Insert a NOP between load instruction and atomic instruction (swap and
casa).
* Insert a NOP at branch target if load in delay slot and atomic
instruction at branch target.
* Do not allow functions to begin with atomic instruction.
GRLIB-TN-0011:
* Insert .p2align 4 before atomic instructions (swap and casa).
GRLIB-TN-0012:
* Place a NOP at the branch target of an integer branch if it is a
floating-point operation or a floating-point branch.
GRLIB-TN-0013:
* Prevent (div/sqrt) instructions in the delay slot.
* Insert NOPs to prevent the sequence (div/sqrt) -> (two or three
floating point operations or loads) -> (div/sqrt).
* Do not insert NOPs if any of the floating point operations have a
dependency on the destination register of the first (div/sqrt).
* Do not insert NOPs if one of the floating point operations is a
(div/sqrt).
* Insert NOPs to prevent (div/sqrt) followed by a branch.
Implement handling for `v8plus` feature bit to allow the user to switch
between V8 and V8+ mode with 32-bit code.
Currently this only sets the appropriate ELF machine type and flags;
codegen changes will be done in future patches.
This is done as a prerequisite for `-mv8plus` flag on clang (#98713).
The parameter is confusing as it duplicates MCStreamer::isVeboseAsm
(initialized from MCTargetOptions::AsmVerbose). After
233cca169237b91d16092c82bd55ee6a283afe98, no in-tree target uses the
parameter.
Well, not quite that simple. We can tc memset since it returns the first
argument but bzero doesn't do that and therefore we can end up
miscompiling.
This patch also refactors the logic out of isInTailCallPosition() into the callers.
As a result memcpy and memmove are also modified to do the same thing
for consistency.
rdar://131419786
Summary:
These Libcalls represent which functions are available to the backend.
If a runtime call is not available, the target sets the the name to
`nullptr`. Currently, this logic is spread around the various targets.
This patch pulls all of the locations that disable libcalls into the
intializer. This patch is effectively NFC.
The motivation behind this patch is that currently the LTO handling uses
the list of all runtime calls to determine which functions cannot be
internalized and must be extracted from static libraries. We do not want
this to happen for libcalls that are not emitted by the backend. A
follow-up patch will move out this logic so the LTO pass can know which
rtlib calls are actually used by the backend.
Validate and reject any unknown or unavailable instruction mnemonics early
in ParseInstruction, before any operand parsing is performed. Some operands
(mainly memory ones) can be parsed slightly differently in V8 and V9
assembly language, so by rejecting unknown or unavailable instructions early
we can prevent the error message from being shadowed by the one raised during
operand parsing.
As a side effect this also allows us to tell unknown and unavailable
mnemonics apart, and issue a suggestion in appropriate cases.
This is based on the approach taken by the MIPS backend.
Reviewers: brad0, rorth, s-barannikov, jrtc27
Reviewed By: s-barannikov
Pull Request: https://github.com/llvm/llvm-project/pull/96021
Emit the correct machine type when writing out ELF objects.
This patch is modeled on GCC's behavior:
- `-m32` emits an object of type EM_SPARC;
- `-m32 -mcpu=v9` emits EM_SPARC32PLUS (however, see below); and
- `-m64` emits EM_SPARCV9.
Note that GCC does not guarantee emission of EM_SPARC32PLUS objects,
since GNU as doesn't support user control of emitted machine type.
It will always autodetect the type based on the instruction mix:
- If there's a V9 instruction inside, then emit EM_SPARC32PLUS; and
- Emit EM_SPARC otherwise.
For LLVM we choose deterministic behavior instead for simplicity.
Unify parts of ASI and Prefetch tag matching at `parseASITag`
and `parsePrefetchTag` to use a common function to parse any immediate
expressions. This introduces a slight regression to error messages,
but is needed so we can enable `ParseForAllFeatures`
in `MatchOperandParserImpl` in a future patch.
Reviewers: jrtc27, brad0, rorth, s-barannikov
Reviewed By: s-barannikov
Pull Request: https://github.com/llvm/llvm-project/pull/96020
This adds the alternate mnemonics for movrz and movrnz.
Reviewers: s-barannikov, jrtc27, brad0, rorth
Reviewed By: s-barannikov
Pull Request: https://github.com/llvm/llvm-project/pull/94252
If the Count passed into writeNopData is not a multiple of four,
add a little amount of zeros before writing the NOP stream.
This makes it match the behavior of GNU binutils.
Reviewers: brad0, rorth, s-barannikov, jrtc27
Reviewed By: s-barannikov
Pull Request: https://github.com/llvm/llvm-project/pull/94251
This adds support for `prefetcha` instruction for prefetching from
alternate address spaces.
Reviewers: jrtc27, brad0, rorth, s-barannikov
Reviewed By: s-barannikov
Pull Request: https://github.com/llvm/llvm-project/pull/94250
This adds named tag constants (such as `#one_write` and `#one_read`)
for the prefetch instruction.
Reviewers: jrtc27, rorth, brad0, s-barannikov
Reviewed By: s-barannikov
Pull Request: https://github.com/llvm/llvm-project/pull/94249
This adds %set_softint and %clear_softint alias for %asr20 and %asr21
as defined in JPS1.
Reviewers: jrtc27, brad0, s-barannikov, rorth
Reviewed By: s-barannikov
Pull Request: https://github.com/llvm/llvm-project/pull/94247
This adds support for GNU %uhi and %ulo extensions.
Those resolve to the same relocations as %hh and %hm.
Reviewers:
cyndyishida, dcci, brad0, jrtc27, aaupov, Endilll, rorth, maksfb, #reviewers-libcxxabi, s-barannikov, rafaelauler, ayermolo, #reviewers-libunwind, #reviewers-libcxx, daniel-grumberg, tbaederr
Reviewed By: s-barannikov
Pull Request: https://github.com/llvm/llvm-project/pull/94246
Transform `addc imm, %rs, %rd` into `addc %rs, imm, %rd`.
This is used in some GNU and Linux code.
Reviewers: s-barannikov, rorth, jrtc27, brad0
Reviewed By: s-barannikov
Pull Request: https://github.com/llvm/llvm-project/pull/94245
- Fix build with `EXPENSIVE_CHECKS`
- Remove unused `PassName::ID` to resolve warning
- Mark `~SelectionDAGISel` virtual so AArch64 backend can work properly
This reverts commit de37c06f01772e02465ccc9f538894c76d89a7a1 to
de37c06f01772e02465ccc9f538894c76d89a7a1
It still breaks EXPENSIVE_CHECKS build. Sorry.
Port selection dag isel to new pass manager.
Only `AMDGPU` and `X86` support new pass version. `-verify-machineinstrs` in new pass manager belongs to verify instrumentation, it is enabled by default.
I'm planning to remove StringRef::equals in favor of
StringRef::operator==.
- StringRef::operator==/!= outnumber StringRef::equals by a factor of
38 under llvm/ in terms of their usage.
- The elimination of StringRef::equals brings StringRef closer to
std::string_view, which has operator== but not equals.
- S == "foo" is more readable than S.equals("foo"), especially for
!Long.Expression.equals("str") vs Long.Expression != "str".
- Those special register stores are STORE and their memory operands are
input operands instead of output ones.
Reviewers:
JDevlieghere, arsenm, yinying-lisa-li, koachan, PeimingLiu, jyknight, aartbik, matthias-springer
Reviewed By: arsenm
Pull Request: https://github.com/llvm/llvm-project/pull/88971
This adds support for using the L and H argument modifiers for twinword
operands in inline asm code, such as in:
```
%1 = tail call i64 asm sideeffect "rd %pc, ${0:L} ; srlx ${0:L}, 32, ${0:H}", "={o4}"()
```
This is needed by the Linux kernel.
When in 32-bit mode, the backend doesn't currently implement 64-bit
atomics, even though the hardware is capable if you have specified a V9
CPU. Thus, limit the width to 32-bit, for now, leaving behind a TODO.
This fixes a regression triggered by PR #73176.
This adds support for marking arbitrary general purpose registers -
except for those with special purpose (G0, I6-I7, O6-O7) - as reserved,
as needed by some software like the Linux kernel.
