7 Commits

Author SHA1 Message Date
Vyacheslav Levytskyy
978de2d666
[SPIR-V] Add saturation and float rounding mode decorations, a subset of arithmetic constrained floating-point intrinsics, and SPV_INTEL_float_controls2 extension (#119862)
This PR adds the following features:
* saturation and float rounding mode decorations,
* arithmetic constrained floating-point intrinsics (strict_fadd,
strict_fsub, strict_fmul, strict_fdiv, strict_frem, strict_fma and
strict_fldexp),
* and SPV_INTEL_float_controls2 extension,
* using recent improvements of emit-intrinsics step, this PR also
simplifies pre- and post-legalizer steps and improves instruction
selection.
2024-12-16 10:29:46 +01:00
Vyacheslav Levytskyy
9b43078e4c
[SPIR-V] Extend support for __spirv_ builtins (#117190)
This PR extends support for `__spirv_` builtins by adding missed
builtins (`GroupNonUniformBroadcast*`) and supporting more "_R<type>"
builtins.
2024-11-21 18:46:33 +01:00
Vyacheslav Levytskyy
f9c98068c8
[SPIR-V] Rework usage of virtual registers' types and classes (#101732)
This PR contains changes in virtual register processing aimed to improve
correctness of emitted MIR between passes from the perspective of
MachineVerifier. This potentially helps to detect previously missed
flaws in code emission and harden the test suite. As a measure of
correctness and usefulness of this PR we may use a mode with expensive
checks set on, and MachineVerifier reports problems in the test suite.

In order to satisfy Machine Verifier requirements to MIR correctness not
only a rework of usage of virtual registers' types and classes is
required, but also corrections into pre-legalizer and instruction
selection logics. Namely, the following changes are introduced:
* scalar virtual registers have proper bit width,
* detect register class by SPIR-V type,
* add a superclass for id virtual register classes,
* fix Tablegen rules used for instruction selection,
* fixes of minor existed issues (missed flag for proper representation
of a null constant for OpenCL vs. HLSL, wrong usage of integer virtual
registers as a synonym of any non-type virtual register).
2024-08-12 15:49:43 +02:00
Vyacheslav Levytskyy
24cee1c41c
[SPIR-V] Add __spirv_ wrappers to Non-Uniform, Atomic, Convert Instructions (#96790)
This PR:
* adds missing __spirv_ wrappers to Non-Uniform, Atomic, and Convert
Instructions,
* fixes emission of Group builtins,
* adds relevant checks to test cases to cover newly added __spirv_
wrappers.
2024-07-04 07:29:21 +02:00
Michal Paszkowski
3a26a65082 [SPIR-V] Disable MachineLateInstrsCleanup pass
This patch disables MachineLateInstrsCleanup pass (since it does not
work with virtual registers) and modifies LIT tests to run with -O0.

Differential Revision: https://reviews.llvm.org/D140103
2022-12-19 19:25:33 +01:00
Andrey Tretyakov
4bd9d98bc2 [SPIRV] Fix style of LIT tests and remove metadata
Fix style, indentation, comments of LIT tests
and remove unnecessary metadata and attributes.

Differential Revision: https://reviews.llvm.org/D130664
2022-08-03 02:33:24 +03:00
Ilia Diachkov
0098f2aebb [SPIRV] Add SPIR-V specific intrinsics, two passes and tests
The patch adds SPIR-V specific intrinsics required to keep information
critical to SPIR-V consistency (types, constants, etc.) during translation
from IR to MIR.

Two related passes (SPIRVEmitIntrinsics and SPIRVPreLegalizer) and several
LIT tests (passed with this change) have also been added.

It also fixes the issue with opaque pointers in SPIRVGlobalRegistry.cpp
and the mismatch of the data layout between the SPIR-V backend and clang
(Issue #55122).

Differential Revision: https://reviews.llvm.org/D124416

Co-authored-by: Aleksandr Bezzubikov <zuban32s@gmail.com>
Co-authored-by: Michal Paszkowski <michal.paszkowski@outlook.com>
Co-authored-by: Andrey Tretyakov <andrey1.tretyakov@intel.com>
Co-authored-by: Konrad Trifunovic <konrad.trifunovic@intel.com>
2022-05-06 03:02:00 +03:00