9919 Commits

Author SHA1 Message Date
Teresa Johnson
1f884ef769 [docs] Document MemProf metadata in LangRef
Add documentation for memprof and callsite metadata in LangRef.

Differential Revision: https://reviews.llvm.org/D146007
2023-03-14 11:04:17 -07:00
aabhinavg
ae2d8def6b [Docs] Added llvm-reduce docs in CommandGuide
[Docs] Added llvm-reduce docs in CommandGuide

Differential Revision: https://reviews.llvm.org/D146020
2023-03-14 20:55:20 +05:30
Nikita Popov
af101f9ae0 [IR] Allow !range on vector of integer instructions
Inspired by https://reviews.llvm.org/D144467#4188310, this allows
!range on vector of integer instructions, with the usual
element-wise interpretation, which is already used by various
analysis APIs that support vectors.

Differential Revision: https://reviews.llvm.org/D145920
2023-03-14 09:41:56 +01:00
aabhinavg
5686364d90 [Docs] Added llvm-mc documentation
Fix #61313

Reviewed By: lattner

Differential Revision: https://reviews.llvm.org/D145844
2023-03-14 08:23:15 +05:30
Joshua Cranmer
bcad161db3 [Clang][SPIR-V] Emit target extension types for OpenCL types on SPIR-V.
Reviewed By: Anastasia

Differential Revision: https://reviews.llvm.org/D141008
2023-03-13 14:20:24 -04:00
Arthur Eubanks
d623b2f95f [PassManagerBuilder] Remove PassManagerBuilder
PassManagerBuilder is dead, long live PassBuilder!

bugpoint's -O# are now useless (and probably have been for a while given the number of passes we've removed from PassManagerBuilder). Perhaps they'll be revived if bugpoint ever works with the new PM.

Reviewed By: nikic, MaskRay

Differential Revision: https://reviews.llvm.org/D145835
2023-03-13 09:30:30 -07:00
Sameer Sahasrabuddhe
fd98416d37 [llvm][Uniformity] consistently handle always-uniform instructions
An instruction that is "always uniform" is so even if it occurs in an
irreducible cycle. The output produced by such an instruction may depend on the
implementation defined cycle hierarchy, but that does not affect the uniformity
of the output. In other words, an "always uniform" instruction is uniform even
if it is not m-converged.

Reviewed By: ruiling, ronlieb

Differential Revision: https://reviews.llvm.org/D145572
2023-03-10 14:23:40 +05:30
Lang Hames
7163b1ab8d [JITLink][docs] Update docs for generic link algorithm and memory manager apis.
These sections were out of date.
2023-03-09 23:37:32 -08:00
Arthur Eubanks
9e0c2626f3 [llvm-c] Remove pointee support from LLVMGetElementType
Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D145717
2023-03-09 15:42:38 -08:00
Arthur Eubanks
ab8d7ea486 [docs] Mention LLVM_USE_LINKER/LLVM_PARALLEL_{COMPILE,LINK}_JOBS in GettingStarted
As requested in D145413.

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D145714
2023-03-09 13:04:15 -08:00
Nikita Popov
7ed77dad81 [LangRef] Use new memory attribute syntax (NFC)
Use the memory() spelling in a few places that were using the
old syntax.

The documented attributes for llvm.type.checked.load don't match
the actual attributes, I've raised this here:
https://reviews.llvm.org/D21121#inline-1406792
2023-03-09 10:21:16 +01:00
Nikita Popov
0aac9a2875 [llvm-c] Remove PassManagerBuilder APIs
The legacy PM is only supported for codegen, and PassManagerBuilder
is exclusively about the middle-end optimization pipeline. Drop it.

Differential Revision: https://reviews.llvm.org/D145387
2023-03-09 09:59:32 +01:00
Arthur Eubanks
65548ff349 [docs] Update README and GettingStarted
Funnel fetching and building LLVM instructions into GettingStarted.

Modernize the build steps a little.

Remove comments saying CMAKE_BUILD_TYPE defaults to Debug as that's not true anymore (must explicitly pass it).

Reviewed By: MaskRay, hans

Differential Revision: https://reviews.llvm.org/D145413
2023-03-08 12:55:59 -08:00
Michael Buch
6a0f0fb190 [ReleaseNotes] Fix formatting for LLDB changes 2023-03-08 15:34:31 +00:00
Alex Bradbury
cac180523e [docs] Document how frequently the staging buildmaster configuration is reconfigured
Differential Revision: https://reviews.llvm.org/D144465
2023-03-08 10:48:01 +00:00
Zain Jaffal
d612a75279
[TableGen] add !toupper and !tolower operators to change the casing of strings.
Reviewed By: fpetrogalli

Differential Revision: https://reviews.llvm.org/D145300
2023-03-07 12:41:56 +00:00
Alex MacLean
8a5d4eb775 [docs][NewPM] fix typos in new pass manager docs
Fix some minor errors in the code-block sections of the new pass manager documentation

Reviewed By: aeubanks

Differential Revision: https://reviews.llvm.org/D145325
2023-03-06 09:17:56 -08:00
Paulo Matos
9f493be7e6 Revert "[Docs] Add my Office Hours"
This reverts commit b293de988059cac25c4ad84371be09107de7bbc4.
2023-03-06 10:51:48 +01:00
Mark de Wever
92523a35a8 Revert "[CMake] Bumps minimum version to 3.20.0."
Some build bots have not been updated to the new minimal CMake version.
Reverting for now and ping the buildbot owners.

This reverts commit 44c6b905f8527635e49bb3ea97dea315f92d38ec.
2023-03-04 18:28:13 +01:00
Mark de Wever
44c6b905f8 [CMake] Bumps minimum version to 3.20.0.
This partly undoes D137724.

This change has been discussed on discourse
https://discourse.llvm.org/t/rfc-upgrading-llvms-minimum-required-cmake-version/66193

Note this does not remove work-arounds for older CMake versions, that
will be done in followup patches.

Reviewed By: mehdi_amini, MaskRay, ChuanqiXu, to268, thieta, tschuett, phosek, #libunwind, #libc_vendors, #libc, #libc_abi, sivachandra, philnik, zibi

Differential Revision: https://reviews.llvm.org/D144509
2023-03-04 12:40:57 +01:00
Vadim Paretsky
56e8fd6f6a [llvm-lib] update ReleaseNotes for llvm-lib's new support for generating
an import library from a definition file

Differential Revision:https://reviews.llvm.org/D145140
2023-03-03 10:54:27 -08:00
Daniel Thornburgh
072e07a9d5 [llvm-cov] Optionally fail on missing binary ID
This adds the --check-binary-id flag that makes sure that an object file
is available for every binary ID mentioned in the given profile. This
should help make the tool more robust in CI environments where it's
expected that coverage mappings should be available for every object
contributing to the profile.

Reviewed By: gulfem

Differential Revision: https://reviews.llvm.org/D144308
2023-03-03 10:24:21 -08:00
Ragavan Dasarathan
ed94ffee97 [Nomination] Adding Nvidia Compiler security representative to the LLVM security group.
I'm from Nvidia Corporation. I work primarily on the Security aspect of Compiler toolchains based out of LLVM. I would like to nominate myself to join the LLVM security group as a vendor contact representative of Nvidia.

According to the information on the website, https://llvm.org/docs/Security.html, I fall under the following category: Vendor contacts.

We are particularly interested in the following:
  - Being aware of any security vulnerability that has been found in the compiler in a timely manner.
  - Correctly reporting any vulnerabilities or other security issues we have found in the compiler stack.
  - Discussing our use of static analysis / dynamic analysis / fuzzing / threat modelling with the committee and raising any concerns that have risen from said activities.

Looking forward to participating in further discussions and security sync ups with the rest of the committee
Please let me know if I need to provide any other information required for this nomination.
Thanks,
Ragavan

Reviewed By: ab, apilipenko, george.burgess.iv, kristof.beyls, mattdr, nikhgupt, probinson, peter.smith, pietroalbini

Differential Revision: https://reviews.llvm.org/D144585
2023-03-03 10:02:37 -08:00
Nick Desaulniers
71a28fb74b [Docs] update MemorySSA for opaque ptrs
Reviewed By: asbirlea, nikic

Differential Revision: https://reviews.llvm.org/D145130
2023-03-02 12:58:58 -08:00
J. Ryan Stinnett
1572742cfa [DebugInfo][Docs] Remove dbg.addr from docs
Part of `dbg.addr` removal
Discussed in https://discourse.llvm.org/t/what-is-the-status-of-dbg-addr/62898

Differential Revision: https://reviews.llvm.org/D144792
2023-03-02 09:29:42 +00:00
Nikita Popov
f7ca013332 [llvm-c] Remove bindings for creating legacy passes
Legacy passes are only supported for codegen, and I don't believe
it's possible to write backends using the C API, so we should drop
all of those. Reduces the number of places that need to be modified
when removing legacy passes.

Differential Revision: https://reviews.llvm.org/D144970
2023-03-02 09:53:50 +01:00
Mitch Phillips
a4d39d4b69 [llvm-readobj] Add --memtag
This adds functionality to readelf/readobj to specifically handle
MTE-related bits, like the AARCH64_MEMTAG_* dynamic entries, and a
decoder for the Android-specific ELF note.

Reviewed By: jhenderson, MaskRay

Differential Revision: https://reviews.llvm.org/D143693
2023-03-01 10:59:59 -08:00
Sander de Smalen
0d94b63604 [IR] Add LLVM IR support for target("aarch64.svcount") type.
The C and C++ Language Extensions for AArch64 SME2 [1] adds a new type called
`svcount_t` which describes a predicate. This is not a predicate vector
mask, but rather a description of a predicate vector mask that can be
expanded into a mask using explicit instructions. The type is a scalable
opaque type.

To implement `svcount_t` type this patch uses the existing Target Extension Type
mechanism, but adds further support so that this type can be a scalable type.

AArch64 CodeGen support will follow in a separate patch.

[1] https://github.com/ARM-software/acle/pull/217

Reviewed By: jcranmer-intel, nikic

Differential Revision: https://reviews.llvm.org/D136861
2023-03-01 08:17:53 +00:00
Lian Wang
bc504e0f06 [Doc][NFC] Add template type when use MachinePassRegistry.
Reviewed By: serge-sans-paille

Differential Revision: https://reviews.llvm.org/D144945
2023-03-01 02:37:21 +00:00
Alan Hu
e0efe46b33 [OCaml] Remove all PassManager-related functions
Reviewed By: aeubanks, nikic

Differential Revision: https://reviews.llvm.org/D144751
2023-02-24 13:14:18 -08:00
Philipp Tomsich
f68f04d07c [RISCV] Add vendor-defined XTheadCondMov (conditional move) extension
The vendor-defined XTheadCondMov (somewhat related to the upcoming
Zicond and XVentanaCondOps) extension add conditional move
instructions with $rd being an input and an ouput instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=73442230966a22b3238b2074691a71d7b4ed914a

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144681
2023-02-24 21:40:42 +01:00
Aaron Ballman
f8f329a224 Fix the LLVM Sphinx build
This addresses the issue found by:
https://lab.llvm.org/buildbot/#/builders/30/builds/32299
2023-02-24 07:57:25 -05:00
Matt Arsenault
c0db240e51 AMDGPU: Document denormal behavior
Not sure this is the right place for it next to the table.
2023-02-24 07:41:29 -04:00
Matt Arsenault
5da674492a IR: Add nofpclass parameter attribute
This carries a bitmask indicating forbidden floating-point value kinds
in the argument or return value. This will enable interprocedural
-ffinite-math-only optimizations. This is primarily to cover the
no-nans and no-infinities cases, but also covers the other floating
point classes for free. Textually, this provides a number of names
corresponding to bits in FPClassTest, e.g.

  call nofpclass(nan inf) @must_be_finite()
  call nofpclass(snan) @cannot_be_snan()

This is more expressive than the existing nnan and ninf fast math
flags. As an added bonus, you can represent fun things like nanf:

  declare nofpclass(inf zero sub norm) float @only_nans()

Compared to nnan/ninf:
  - Can be applied to individual call operands as well as the return value
  - Can distinguish signaling and quiet nans
  - Distinguishes the sign of infinities
  - Can be safely propagated since it doesn't imply anything about
    other operands.
  - Does not apply to FP instructions; it's not a flag

This is one step closer to being able to retire "no-nans-fp-math" and
"no-infs-fp-math". The one remaining situation where we have no way to
represent no-nans/infs is for loads (if we wanted to solve this we
could introduce !nofpclass metadata, following along with
noundef/!noundef).

This is to help simplify the GPU builtin math library
distribution. Currently the library code has explicit finite math only
checks, read from global constants the compiler driver needs to set
based on the compiler flags during linking. We end up having to
internalize the library into each translation unit in case different
linked modules have different math flags. By propagating known-not-nan
and known-not-infinity information, we can automatically prune the
edge case handling in most functions if the function is only reached
from fast math uses.
2023-02-24 07:41:29 -04:00
Michael Liao
fe6ca54682 [LangRef] Correct value ranges for address space, vector, and float bit sizes.
- The current implementation checks them for 24-bit inegers but the
  document says 23-bit one effectively by listing the range as [1,2^23).
- Minor error message correction.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D144685
2023-02-23 21:54:50 -05:00
Manolis Tsamis
7b79e8d455 [RISCV] Add vendor-defined XTheadFMemIdx (FP Indexed Memory Operations) extension
The vendor-defined XTHeadFMemIdx (no comparable standard extension exists
at the time of writing) extension adds indexed load/store instructions
for floating-point registers.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=f511f80fa3fcaf6bcbe727fb902b8bd5ec8f9c20

Depends on D144249

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144647
2023-02-24 00:35:37 +01:00
Manolis Tsamis
f6262201d8 [RISCV] Add vendor-defined XTheadMemIdx (Indexed Memory Operations) extension
The vendor-defined XTHeadMemIdx (no comparable standard extension exists
at the time of writing) extension adds indexed load/store instructions
as well as load/store and update register instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=27cfd142d0a7e378d19aa9a1278e2137f849b71b

Depends on D144002

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144249
2023-02-24 00:17:58 +01:00
Manolis Tsamis
16a6cf6a99 [RISCV] Add vendor-defined XTheadSync (Multi-core synchronization) extension
The vendor-defined XTheadSync (no comparable standard extension exists
at the time of writing) extension adds multi-core synchronization
instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=547c18d9bb95571261dbd17f4767194037eb82bd

Depends on D144496

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144501
2023-02-22 11:15:40 +01:00
Manolis Tsamis
f5b484c56f [RISCV] Add vendor-defined XTheadCmo (Cache Management Operations) extension
The vendor-defined XTHeadCmo (there are some similarities with the
Zicbom standard extension) extension adds cache management instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=a9ba8bc2d396fb8ae2b892f3bc6be8cdfe4b555c

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144496
2023-02-22 10:57:48 +01:00
Alex Bradbury
50613578d9 [docs] Improve guidance on installing the correct buildbot-worker version
The docs currently state that buildbot-worker 2.8.5 is used. However,
looking at the buildbot release notes
<http://docs.buildbot.net/current/relnotes/index.html>, this release
doesn't seem to exist (it's not on PyPI either). The document also links
to http://trac.buildbot.net/ as a source to retrieve an old version and
install it manually, but this is dead.

Instead, drop that advice and suggest pip3 install
buildbot-worker==2.8.4, as done by the Dockerfiles in
llvm-zorg/buildbot/google/docker/*.

Differential Revision: https://reviews.llvm.org/D144464
2023-02-21 18:39:42 +00:00
Manolis Tsamis
bbb58a2302 [RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension
The vendor-defined XTHeadMemPair (no comparable standard extension exists
at the time of writing) extension adds two-GPR load/store pair instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=6e17ae625570ff8f3c12c8765b8d45d4db8694bd

Depends on D143847

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144002
2023-02-21 12:21:49 +01:00
Felipe de Azevedo Piovezan
997dc7e00f [debug-info][codegen] Prevent creation of self-referential SP node
The function `CGDebugInfo::EmitFunctionDecl` is supposed to create a
declaration -- never a _definition_ -- of a subprogram. This is made
evident by the fact that the SPFlags never have the "Declaration" bit
set by that function.

However, when `EmitFunctionDecl` calls `DIBuilder::createFunction`, it
still tries to fill the "Declaration" argument by passing it the result
of `getFunctionDeclaration(D)`. This will query an internal cache of
previously created declarations and, for most code paths, we return
nullptr; all is good.

However, as reported in [0], there are pathological cases in which we
attempt to recreate a declaration, so the cache query succeeds,
resulting in a subprogram declaration whose declaration field points to
another declaration. Through a series of RAUWs, the declaration field
ends up pointing to the SP itself. Self-referential MDNodes can't be
`unique`, which causes the verifier to fail (declarations must be
`unique`).

We can argue that the caller should check the cache first, but this is
not a correctness issue (declarations are `unique` anyway). The bug is
that `CGDebugInfo::EmitFunctionDecl` should always pass `nullptr` to the
declaration argument of `DIBuilder::createFunction`, expressing the fact
that declarations don't point to other declarations. AFAICT this is not
something for which any reasonable meaning exists.

This seems a lot like a copy-paste mistake that has survived for ~10
years, since other places in this file have the exact same call almost
token-by-token.

I've tested this by compiling LLVMSupport with and without the patch, O2
and O0, and comparing the dwarfdump of the lib. The dumps are identical
modulo the attributes decl_file/producer/comp_dir.

[0]: https://github.com/llvm/llvm-project/issues/59241

Differential Revision: https://reviews.llvm.org/D143921
2023-02-20 14:22:49 -05:00
Aaron Ballman
8b3091b4b4 Fix LLVM sphinx build
This fixes the issue found by:
https://lab.llvm.org/buildbot/#/builders/30/builds/32127
2023-02-20 08:35:42 -05:00
Caroline Concatto
d515ecca68 [IR] Add new intrinsics interleave and deinterleave vectors
This patch adds 2 new intrinsics:

  ; Interleave two vectors into a wider vector
  <vscale x 4 x i64> @llvm.vector.interleave2.nxv2i64(<vscale x 2 x i64> %even, <vscale x 2 x i64> %odd)

  ; Deinterleave the odd and even lanes from a wider vector
  {<vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.vector.deinterleave2.nxv2i64(<vscale x 4 x i64> %vec)

The main motivator for adding these intrinsics is to support vectorization of
complex types using scalable vectors.

The intrinsics are kept simple by only supporting a stride of 2, which makes
them easy to lower and type-legalize. A stride of 2 is sufficient to handle
complex types which only have a real/imaginary component.

The format of the intrinsics matches how `shufflevector` is used in
LoopVectorize. For example:

  using cf = std::complex<float>;

  void foo(cf * dst, int N) {
      for (int i=0; i<N; ++i)
          dst[i] += cf(1.f, 2.f);
  }

For this loop, LoopVectorize:
  (1) Loads a wide vector (e.g. <8 x float>)
  (2) Extracts odd lanes using shufflevector (leading to <4 x float>)
  (3) Extracts even lanes using shufflevector (leading to <4 x float>)
  (4) Performs the addition
  (5) Interleaves the two <4 x float> vectors into a single <8 x float> using
      shufflevector
  (6) Stores the wide vector.

In this example, we can 1-1 replace shufflevector in (2) and (3) with the
deinterleave intrinsic, and replace the shufflevector in (5) with the
interleave intrinsic.

The SelectionDAG nodes might be extended to support higher strides (3, 4, etc)
as well in the future.

Similar to what was done for vector.splice and vector.reverse, the intrinsic
is lowered to a shufflevector when the type is fixed width, so to benefit from
existing code that was written to recognize/optimize shufflevector patterns.

Note that this approach does not prevent us from adding new intrinsics for other
strides, or adding a more generic shuffle intrinsic in the future. It just solves
the immediate problem of being able to vectorize loops with complex math.

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D141924
2023-02-20 12:21:59 +00:00
Alex Bradbury
d41a73aa94 [RISCV][MC] Mark Zawrs extension as non-experimental
Support for the unratified 1.0-rc3 specification was introduced in
D133443. The specification has since been ratified (in November 2022
according to the recently ratified extensions list
<https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions>.

A review of the diff
<https://github.com/riscv/riscv-zawrs/compare/V1.0-rc3...main> of the
1.0-rc3 spec vs the current/ratified document shows no changes to the
instruction encoding or naming. At one point, a note was added
<e84f42406a>
indicating Zawrs depends on the Zalrsc extension (not officially
specified, but I believe to be just the LR/SC instructions from the A
extension). The final text ended up as "The instructions in the Zawrs
extension are only useful in conjunction with the LR instructions, which
are provided by the A extension, and which we also expect to be provided
by a narrower Zalrsc extension in the future." I think it's consistent
with this phrasing to not require the A extension for Zawrs, which
matches what was implemented.

No intrinsics are implemented for Zawrs currently, meaning we don't need
to additionally review whether those intrinsics can be considered
finalised and ready for exposure to end users.

Differential Revision: https://reviews.llvm.org/D143507
2023-02-19 20:43:03 +00:00
eopXD
b531192254 [Doc] Fix type-o under LangRef
Signed-off-by: eop Chen <eop.chen@sifive.com>
2023-02-18 02:12:24 -08:00
Daniel Thornburgh
8007bcc13f [llvm-cov] Create syntax to pass source w/o binary.
Since binary ID lookup makes CLI object arguments optional, it should be
possible to pass a list of source files without a binary. Unfortunately,
the current syntax will always interpret the first source file as a
binary. This change adds a `-sources` option to cause all later
positional arguments to be considered sources.

Reviewed By: gulfem

Differential Revision: https://reviews.llvm.org/D144207
2023-02-17 13:11:54 -08:00
Philipp Tomsich
16a66af0a0 Revert "[RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension"
This reverts commit d2918544a7fc4b5443879fe12f32a712e6dfe325.
2023-02-17 19:45:55 +01:00
Manolis Tsamis
d2918544a7 [RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension
The vendor-defined XTHeadMemPair (no comparable standard extension exists
at the time of writing) extension adds two-GPR load/store pair instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=6e17ae625570ff8f3c12c8765b8d45d4db8694bd

Depends on D143847

Differential Revision: https://reviews.llvm.org/D144002
2023-02-17 19:45:22 +01:00
Jun Sha (Joshua)
c0947dc441 [RISCV][MC] Add support for experimental zfa extension (FLI instruction not included) (try 3)
(Opening comment by preames - submitter, not patch author)

Try 1 was reverted because it had been landed in pieces, none of which had a meaningful commit message.

Try 2 was reverted because of a buildbot failure.  It turns out this was a spurious revert on my (preames) part.  The buildbots were failing, and it was from one of my changes in this sequence, but not the recommit.  I had reverted both of the try 1 commits in a single git push, but in separate *commits*.  Some of the builders decided to build the broken state between the original try 1 commit, and I'd not noticed that.  I'd assumed the breakage was because of the try2 re-commit.  So the revert of the try 2 recommit was spurious.

Original commit message:

This implements experimental support for the RISCV Zfa extension as specified here: https://github.com/riscv/riscv-isa-manual/releases/download/draft-20221119-5234c63/riscv-spec.pdf, Ch. 25. This extension has not been ratified. Once ratified, it'll move out of experimental status.

This change adds assembly support for all instructions except load-immediate instructions (fli.s/fli.d/fli.h).  Assembly support for that instruction and codegen support will follow in separate patches.

Differential Revision: https://reviews.llvm.org/D141984
2023-02-17 09:34:36 -08:00